UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h

   1 /** @file
   2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
   3
   4 Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_PISMMCPUDXESMM_H_
  16 #define _CPU_PISMMCPUDXESMM_H_
  17
  18 #include <PiSmm.h>
  19
  20 #include <Protocol/MpService.h>
  21 #include <Protocol/SmmConfiguration.h>
  22 #include <Protocol/SmmCpu.h>
  23 #include <Protocol/SmmAccess2.h>
  24 #include <Protocol/SmmReadyToLock.h>
  25 #include <Protocol/SmmCpuService.h>
  26
  27 #include <Guid/AcpiS3Context.h>
  28
  29 #include <Library/BaseLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32 #include <Library/SynchronizationLib.h>
  33 #include <Library/DebugLib.h>
  34 #include <Library/BaseMemoryLib.h>
  35 #include <Library/PcdLib.h>
  36 #include <Library/CacheMaintenanceLib.h>
  37 #include <Library/MtrrLib.h>
  38 #include <Library/SmmCpuPlatformHookLib.h>
  39 #include <Library/SmmServicesTableLib.h>
  40 #include <Library/MemoryAllocationLib.h>
  41 #include <Library/UefiBootServicesTableLib.h>
  42 #include <Library/UefiRuntimeServicesTableLib.h>
  43 #include <Library/DebugAgentLib.h>
  44 #include <Library/HobLib.h>
  45 #include <Library/LocalApicLib.h>
  46 #include <Library/UefiCpuLib.h>
  47 #include <Library/CpuExceptionHandlerLib.h>
  48 #include <Library/ReportStatusCodeLib.h>
  49 #include <Library/SmmCpuFeaturesLib.h>
  50 #include <Library/PeCoffGetEntryPointLib.h>
  51
  52 #include <AcpiCpuData.h>
  53 #include <CpuHotPlugData.h>
  54
  55 #include <Register/Cpuid.h>
  56
  57 #include "CpuService.h"
  58 #include "SmmProfile.h"
  59
  60 //
  61 // MSRs required for configuration of SMM Code Access Check
  62 //
  63 #define EFI_MSR_SMM_MCA_CAP                    0x17D
  64 #define  SMM_CODE_ACCESS_CHK_BIT               BIT58
  65
  66 #define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0
  67 #define  SMM_CODE_CHK_EN_BIT                   BIT2
  68
  69 ///
  70 /// Page Table Entry
  71 ///
  72 #define IA32_PG_P                   BIT0
  73 #define IA32_PG_RW                  BIT1
  74 #define IA32_PG_WT                  BIT3
  75 #define IA32_PG_CD                  BIT4
  76 #define IA32_PG_A                   BIT5
  77 #define IA32_PG_PS                  BIT7
  78 #define IA32_PG_PAT_2M              BIT12
  79 #define IA32_PG_PAT_4K              IA32_PG_PS
  80 #define IA32_PG_PMNT                BIT62
  81 #define IA32_PG_NX                  BIT63
  82
  83 //
  84 // Size of Task-State Segment defined in IA32 Manual
  85 //
  86 #define TSS_SIZE              104
  87 #define TSS_X64_IST1_OFFSET   36
  88 #define TSS_IA32_CR3_OFFSET   28
  89 #define TSS_IA32_ESP_OFFSET   56
  90
  91 //
  92 // Code select value
  93 //
  94 #define PROTECT_MODE_CODE_SEGMENT          0x08
  95 #define LONG_MODE_CODE_SEGMENT             0x38
  96
  97 //
  98 // The size 0x20 must be bigger than
  99 // the size of template code of SmmInit. Currently,
 100 // the size of SmmInit requires the 0x16 Bytes buffer
 101 // at least.
 102 //
 103 #define BACK_BUF_SIZE  0x20
 104
 105 #define EXCEPTION_VECTOR_NUMBER     0x20
 106
 107 #define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
 108
 109 typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;
 110 #define ARRIVAL_EXCEPTION_BLOCKED           0x1
 111 #define ARRIVAL_EXCEPTION_DELAYED           0x2
 112 #define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4
 113
 114 //
 115 // Private structure for the SMM CPU module that is stored in DXE Runtime memory
 116 // Contains the SMM Configuration Protocols that is produced.
 117 // Contains a mix of DXE and SMM contents.  All the fields must be used properly.
 118 //
 119 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')
 120
 121 typedef struct {
 122   UINTN                           Signature;
 123
 124   EFI_HANDLE                      SmmCpuHandle;
 125
 126   EFI_PROCESSOR_INFORMATION       *ProcessorInfo;
 127   SMM_CPU_OPERATION               *Operation;
 128   UINTN                           *CpuSaveStateSize;
 129   VOID                            **CpuSaveState;
 130
 131   EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];
 132   EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;
 133   EFI_SMM_ENTRY_POINT             SmmCoreEntry;
 134
 135   EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;
 136 } SMM_CPU_PRIVATE_DATA;
 137
 138 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;
 139 extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;
 140 extern UINTN                  mMaxNumberOfCpus;
 141 extern UINTN                  mNumberOfCpus;
 142 extern BOOLEAN                mRestoreSmmConfigurationInS3;
 143 extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;
 144
 145 ///
 146 /// The mode of the CPU at the time an SMI occurs
 147 ///
 148 extern UINT8  mSmmSaveStateRegisterLma;
 149
 150
 151 //
 152 // SMM CPU Protocol function prototypes.
 153 //
 154
 155 /**
 156   Read information from the CPU save state.
 157
 158   @param  This      EFI_SMM_CPU_PROTOCOL instance
 159   @param  Width     The number of bytes to read from the CPU save state.
 160   @param  Register  Specifies the CPU register to read form the save state.
 161   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 162   @param  Buffer    Upon return, this holds the CPU register value read from the save state.
 163
 164   @retval EFI_SUCCESS   The register was read from Save State
 165   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 166   @retval EFI_INVALID_PARAMTER   This or Buffer is NULL.
 167
 168 **/
 169 EFI_STATUS
 170 EFIAPI
 171 SmmReadSaveState (
 172   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 173   IN UINTN                              Width,
 174   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 175   IN UINTN                              CpuIndex,
 176   OUT VOID                              *Buffer
 177   );
 178
 179 /**
 180   Write data to the CPU save state.
 181
 182   @param  This      EFI_SMM_CPU_PROTOCOL instance
 183   @param  Width     The number of bytes to read from the CPU save state.
 184   @param  Register  Specifies the CPU register to write to the save state.
 185   @param  CpuIndex  Specifies the zero-based index of the CPU save state
 186   @param  Buffer    Upon entry, this holds the new CPU register value.
 187
 188   @retval EFI_SUCCESS   The register was written from Save State
 189   @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
 190   @retval EFI_INVALID_PARAMTER   ProcessorIndex or Width is not correct
 191
 192 **/
 193 EFI_STATUS
 194 EFIAPI
 195 SmmWriteSaveState (
 196   IN CONST EFI_SMM_CPU_PROTOCOL         *This,
 197   IN UINTN                              Width,
 198   IN EFI_SMM_SAVE_STATE_REGISTER        Register,
 199   IN UINTN                              CpuIndex,
 200   IN CONST VOID                         *Buffer
 201   );
 202
 203 /**
 204 Read a CPU Save State register on the target processor.
 205
 206 This function abstracts the differences that whether the CPU Save State register is in the
 207 IA32 CPU Save State Map or X64 CPU Save State Map.
 208
 209 This function supports reading a CPU Save State register in SMBase relocation handler.
 210
 211 @param[in]  CpuIndex       Specifies the zero-based index of the CPU save state.
 212 @param[in]  RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 213 @param[in]  Width          The number of bytes to read from the CPU save state.
 214 @param[out] Buffer         Upon return, this holds the CPU register value read from the save state.
 215
 216 @retval EFI_SUCCESS           The register was read from Save State.
 217 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 218 @retval EFI_INVALID_PARAMTER  This or Buffer is NULL.
 219
 220 **/
 221 EFI_STATUS
 222 EFIAPI
 223 ReadSaveStateRegister (
 224   IN UINTN                        CpuIndex,
 225   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 226   IN UINTN                        Width,
 227   OUT VOID                        *Buffer
 228   );
 229
 230 /**
 231 Write value to a CPU Save State register on the target processor.
 232
 233 This function abstracts the differences that whether the CPU Save State register is in the
 234 IA32 CPU Save State Map or X64 CPU Save State Map.
 235
 236 This function supports writing a CPU Save State register in SMBase relocation handler.
 237
 238 @param[in] CpuIndex       Specifies the zero-based index of the CPU save state.
 239 @param[in] RegisterIndex  Index into mSmmCpuWidthOffset[] look up table.
 240 @param[in] Width          The number of bytes to read from the CPU save state.
 241 @param[in] Buffer         Upon entry, this holds the new CPU register value.
 242
 243 @retval EFI_SUCCESS           The register was written to Save State.
 244 @retval EFI_NOT_FOUND         The register is not defined for the Save State of Processor.
 245 @retval EFI_INVALID_PARAMTER  ProcessorIndex or Width is not correct.
 246
 247 **/
 248 EFI_STATUS
 249 EFIAPI
 250 WriteSaveStateRegister (
 251   IN UINTN                        CpuIndex,
 252   IN EFI_SMM_SAVE_STATE_REGISTER  Register,
 253   IN UINTN                        Width,
 254   IN CONST VOID                   *Buffer
 255   );
 256
 257 //
 258 //
 259 //
 260 typedef struct {
 261   UINT32                            Offset;
 262   UINT16                            Segment;
 263   UINT16                            Reserved;
 264 } IA32_FAR_ADDRESS;
 265
 266 extern IA32_FAR_ADDRESS             gSmmJmpAddr;
 267
 268 extern CONST UINT8                  gcSmmInitTemplate[];
 269 extern CONST UINT16                 gcSmmInitSize;
 270 extern UINT32                       gSmmCr0;
 271 extern UINT32                       gSmmCr3;
 272 extern UINT32                       gSmmCr4;
 273 extern UINTN                        gSmmInitStack;
 274
 275 /**
 276   Semaphore operation for all processor relocate SMMBase.
 277 **/
 278 VOID
 279 EFIAPI
 280 SmmRelocationSemaphoreComplete (
 281   VOID
 282   );
 283
 284 ///
 285 /// The type of SMM CPU Information
 286 ///
 287 typedef struct {
 288   SPIN_LOCK                         Busy;
 289   volatile EFI_AP_PROCEDURE         Procedure;
 290   volatile VOID                     *Parameter;
 291   volatile UINT32                   Run;
 292   volatile BOOLEAN                  Present;
 293 } SMM_CPU_DATA_BLOCK;
 294
 295 typedef enum {
 296   SmmCpuSyncModeTradition,
 297   SmmCpuSyncModeRelaxedAp,
 298   SmmCpuSyncModeMax
 299 } SMM_CPU_SYNC_MODE;
 300
 301 typedef struct {
 302   //
 303   // Pointer to an array. The array should be located immediately after this structure
 304   // so that UC cache-ability can be set together.
 305   //
 306   SMM_CPU_DATA_BLOCK            *CpuData;
 307   volatile UINT32               Counter;
 308   volatile UINT32               BspIndex;
 309   volatile BOOLEAN              InsideSmm;
 310   volatile BOOLEAN              AllCpusInSync;
 311   volatile SMM_CPU_SYNC_MODE    EffectiveSyncMode;
 312   volatile BOOLEAN              SwitchBsp;
 313   volatile BOOLEAN              *CandidateBsp;
 314 } SMM_DISPATCHER_MP_SYNC_DATA;
 315
 316 typedef struct {
 317   SPIN_LOCK    SpinLock;
 318   UINT32       MsrIndex;
 319 } MP_MSR_LOCK;
 320
 321 #define SMM_PSD_OFFSET              0xfb00
 322
 323 typedef struct {
 324   UINT64                            Signature;              // Offset 0x00
 325   UINT16                            Reserved1;              // Offset 0x08
 326   UINT16                            Reserved2;              // Offset 0x0A
 327   UINT16                            Reserved3;              // Offset 0x0C
 328   UINT16                            SmmCs;                  // Offset 0x0E
 329   UINT16                            SmmDs;                  // Offset 0x10
 330   UINT16                            SmmSs;                  // Offset 0x12
 331   UINT16                            SmmOtherSegment;        // Offset 0x14
 332   UINT16                            Reserved4;              // Offset 0x16
 333   UINT64                            Reserved5;              // Offset 0x18
 334   UINT64                            Reserved6;              // Offset 0x20
 335   UINT64                            Reserved7;              // Offset 0x28
 336   UINT64                            SmmGdtPtr;              // Offset 0x30
 337   UINT32                            SmmGdtSize;             // Offset 0x38
 338   UINT32                            Reserved8;              // Offset 0x3C
 339   UINT64                            Reserved9;              // Offset 0x40
 340   UINT64                            Reserved10;             // Offset 0x48
 341   UINT16                            Reserved11;             // Offset 0x50
 342   UINT16                            Reserved12;             // Offset 0x52
 343   UINT32                            Reserved13;             // Offset 0x54
 344   UINT64                            MtrrBaseMaskPtr;        // Offset 0x58
 345 } PROCESSOR_SMM_DESCRIPTOR;
 346
 347 extern IA32_DESCRIPTOR                     gcSmiGdtr;
 348 extern IA32_DESCRIPTOR                     gcSmiIdtr;
 349 extern VOID                                *gcSmiIdtrPtr;
 350 extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;
 351 extern UINT64                              gPhyMask;
 352 extern ACPI_CPU_DATA                       mAcpiCpuData;
 353 extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;
 354 extern VOID                                *mGdtForAp;
 355 extern VOID                                *mIdtForAp;
 356 extern VOID                                *mMachineCheckHandlerForAp;
 357 extern UINTN                               mSmmStackArrayBase;
 358 extern UINTN                               mSmmStackArrayEnd;
 359 extern UINTN                               mSmmStackSize;
 360 extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;
 361 extern IA32_DESCRIPTOR                     gcSmiInitGdtr;
 362
 363 /**
 364   Create 4G PageTable in SMRAM.
 365
 366   @param          ExtraPages       Additional page numbers besides for 4G memory
 367   @return         PageTable Address
 368
 369 **/
 370 UINT32
 371 Gen4GPageTable (
 372   IN      UINTN                     ExtraPages
 373   );
 374
 375
 376 /**
 377   Initialize global data for MP synchronization.
 378
 379   @param Stacks       Base address of SMI stack buffer for all processors.
 380   @param StackSize    Stack size for each processor in SMM.
 381
 382 **/
 383 UINT32
 384 InitializeMpServiceData (
 385   IN VOID        *Stacks,
 386   IN UINTN       StackSize
 387   );
 388
 389 /**
 390   Initialize Timer for SMM AP Sync.
 391
 392 **/
 393 VOID
 394 InitializeSmmTimer (
 395   VOID
 396   );
 397
 398 /**
 399   Start Timer for SMM AP Sync.
 400
 401 **/
 402 UINT64
 403 EFIAPI
 404 StartSyncTimer (
 405   VOID
 406   );
 407
 408 /**
 409   Check if the SMM AP Sync timer is timeout.
 410
 411   @param Timer  The start timer from the begin.
 412
 413 **/
 414 BOOLEAN
 415 EFIAPI
 416 IsSyncTimerTimeout (
 417   IN      UINT64                    Timer
 418   );
 419
 420 /**
 421   Initialize IDT for SMM Stack Guard.
 422
 423 **/
 424 VOID
 425 EFIAPI
 426 InitializeIDTSmmStackGuard (
 427   VOID
 428   );
 429
 430 /**
 431   Initialize Gdt for all processors.
 432
 433   @param[in]   Cr3          CR3 value.
 434   @param[out]  GdtStepSize  The step size for GDT table.
 435
 436   @return GdtBase for processor 0.
 437           GdtBase for processor X is: GdtBase + (GdtStepSize * X)
 438 **/
 439 VOID *
 440 InitGdt (
 441   IN  UINTN  Cr3,
 442   OUT UINTN  *GdtStepSize
 443   );
 444
 445 /**
 446
 447   Register the SMM Foundation entry point.
 448
 449   @param          This              Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
 450   @param          SmmEntryPoint     SMM Foundation EntryPoint
 451
 452   @retval         EFI_SUCCESS       Successfully to register SMM foundation entry point
 453
 454 **/
 455 EFI_STATUS
 456 EFIAPI
 457 RegisterSmmEntry (
 458   IN CONST EFI_SMM_CONFIGURATION_PROTOCOL  *This,
 459   IN EFI_SMM_ENTRY_POINT                   SmmEntryPoint
 460   );
 461
 462 /**
 463   Create PageTable for SMM use.
 464
 465   @return     PageTable Address
 466
 467 **/
 468 UINT32
 469 SmmInitPageTable (
 470   VOID
 471   );
 472
 473 /**
 474   Schedule a procedure to run on the specified CPU.
 475
 476   @param   Procedure        The address of the procedure to run
 477   @param   CpuIndex         Target CPU number
 478   @param   ProcArguments    The parameter to pass to the procedure
 479
 480   @retval   EFI_INVALID_PARAMETER    CpuNumber not valid
 481   @retval   EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 482   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 483   @retval   EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 484   @retval   EFI_SUCCESS - The procedure has been successfully scheduled
 485
 486 **/
 487 EFI_STATUS
 488 EFIAPI
 489 SmmStartupThisAp (
 490   IN      EFI_AP_PROCEDURE          Procedure,
 491   IN      UINTN                     CpuIndex,
 492   IN OUT  VOID                      *ProcArguments OPTIONAL
 493   );
 494
 495 /**
 496   Schedule a procedure to run on the specified CPU in a blocking fashion.
 497
 498   @param  Procedure                The address of the procedure to run
 499   @param  CpuIndex                 Target CPU Index
 500   @param  ProcArguments            The parameter to pass to the procedure
 501
 502   @retval EFI_INVALID_PARAMETER    CpuNumber not valid
 503   @retval EFI_INVALID_PARAMETER    CpuNumber specifying BSP
 504   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber did not enter SMM
 505   @retval EFI_INVALID_PARAMETER    The AP specified by CpuNumber is busy
 506   @retval EFI_SUCCESS              The procedure has been successfully scheduled
 507
 508 **/
 509 EFI_STATUS
 510 EFIAPI
 511 SmmBlockingStartupThisAp (
 512   IN      EFI_AP_PROCEDURE          Procedure,
 513   IN      UINTN                     CpuIndex,
 514   IN OUT  VOID                      *ProcArguments OPTIONAL
 515   );
 516
 517 /**
 518   Initialize MP synchronization data.
 519
 520 **/
 521 VOID
 522 EFIAPI
 523 InitializeMpSyncData (
 524   VOID
 525   );
 526
 527 /**
 528
 529   Find out SMRAM information including SMRR base and SMRR size.
 530
 531   @param          SmrrBase          SMRR base
 532   @param          SmrrSize          SMRR size
 533
 534 **/
 535 VOID
 536 FindSmramInfo (
 537   OUT UINT32   *SmrrBase,
 538   OUT UINT32   *SmrrSize
 539   );
 540
 541 /**
 542   The function is invoked before SMBASE relocation in S3 path to restores CPU status.
 543
 544   The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
 545   and restores MTRRs for both BSP and APs.
 546
 547 **/
 548 VOID
 549 EarlyInitializeCpu (
 550   VOID
 551   );
 552
 553 /**
 554   The function is invoked after SMBASE relocation in S3 path to restores CPU status.
 555
 556   The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
 557   data saved by normal boot path for both BSP and APs.
 558
 559 **/
 560 VOID
 561 InitializeCpu (
 562   VOID
 563   );
 564
 565 /**
 566   Page Fault handler for SMM use.
 567
 568   @param  InterruptType    Defines the type of interrupt or exception that
 569                            occurred on the processor.This parameter is processor architecture specific.
 570   @param  SystemContext    A pointer to the processor context when
 571                            the interrupt occurred on the processor.
 572 **/
 573 VOID
 574 EFIAPI
 575 SmiPFHandler (
 576     IN EFI_EXCEPTION_TYPE   InterruptType,
 577     IN EFI_SYSTEM_CONTEXT   SystemContext
 578   );
 579
 580 /**
 581   Perform the remaining tasks.
 582
 583 **/
 584 VOID
 585 PerformRemainingTasks (
 586   VOID
 587   );
 588
 589 /**
 590   Perform the pre tasks.
 591
 592 **/
 593 VOID
 594 PerformPreTasks (
 595   VOID
 596   );
 597
 598 /**
 599   Initialize MSR spin lock by MSR index.
 600
 601   @param  MsrIndex       MSR index value.
 602
 603 **/
 604 VOID
 605 InitMsrSpinLockByIndex (
 606   IN UINT32      MsrIndex
 607   );
 608
 609 /**
 610   Hook return address of SMM Save State so that semaphore code
 611   can be executed immediately after AP exits SMM to indicate to
 612   the BSP that an AP has exited SMM after SMBASE relocation.
 613
 614   @param[in] CpuIndex     The processor index.
 615   @param[in] RebasedFlag  A pointer to a flag that is set to TRUE
 616                           immediately after AP exits SMM.
 617
 618 **/
 619 VOID
 620 SemaphoreHook (
 621   IN UINTN             CpuIndex,
 622   IN volatile BOOLEAN  *RebasedFlag
 623   );
 624
 625 /**
 626 Configure SMM Code Access Check feature for all processors.
 627 SMM Feature Control MSR will be locked after configuration.
 628 **/
 629 VOID
 630 ConfigSmmCodeAccessCheck (
 631   VOID
 632   );
 633
 634 /**
 635   Hook the code executed immediately after an RSM instruction on the currently
 636   executing CPU.  The mode of code executed immediately after RSM must be
 637   detected, and the appropriate hook must be selected.  Always clear the auto
 638   HALT restart flag if it is set.
 639
 640   @param[in] CpuIndex                 The processor index for the currently
 641                                       executing CPU.
 642   @param[in] CpuState                 Pointer to SMRAM Save State Map for the
 643                                       currently executing CPU.
 644   @param[in] NewInstructionPointer32  Instruction pointer to use if resuming to
 645                                       32-bit mode from 64-bit SMM.
 646   @param[in] NewInstructionPointer    Instruction pointer to use if resuming to
 647                                       same mode as SMM.
 648
 649   @retval The value of the original instruction pointer before it was hooked.
 650
 651 **/
 652 UINT64
 653 EFIAPI
 654 HookReturnFromSmm (
 655   IN UINTN              CpuIndex,
 656   SMRAM_SAVE_STATE_MAP  *CpuState,
 657   UINT64                NewInstructionPointer32,
 658   UINT64                NewInstructionPointer
 659   );
 660
 661 /**
 662   Get the size of the SMI Handler in bytes.
 663
 664   @retval The size, in bytes, of the SMI Handler.
 665
 666 **/
 667 UINTN
 668 EFIAPI
 669 GetSmiHandlerSize (
 670   VOID
 671   );
 672
 673 /**
 674   Install the SMI handler for the CPU specified by CpuIndex.  This function
 675   is called by the CPU that was elected as monarch during System Management
 676   Mode initialization.
 677
 678   @param[in] CpuIndex   The index of the CPU to install the custom SMI handler.
 679                         The value must be between 0 and the NumberOfCpus field
 680                         in the System Management System Table (SMST).
 681   @param[in] SmBase     The SMBASE address for the CPU specified by CpuIndex.
 682   @param[in] SmiStack   The stack to use when an SMI is processed by the
 683                         the CPU specified by CpuIndex.
 684   @param[in] StackSize  The size, in bytes, if the stack used when an SMI is
 685                         processed by the CPU specified by CpuIndex.
 686   @param[in] GdtBase    The base address of the GDT to use when an SMI is
 687                         processed by the CPU specified by CpuIndex.
 688   @param[in] GdtSize    The size, in bytes, of the GDT used when an SMI is
 689                         processed by the CPU specified by CpuIndex.
 690   @param[in] IdtBase    The base address of the IDT to use when an SMI is
 691                         processed by the CPU specified by CpuIndex.
 692   @param[in] IdtSize    The size, in bytes, of the IDT used when an SMI is
 693                         processed by the CPU specified by CpuIndex.
 694   @param[in] Cr3        The base address of the page tables to use when an SMI
 695                         is processed by the CPU specified by CpuIndex.
 696 **/
 697 VOID
 698 EFIAPI
 699 InstallSmiHandler (
 700   IN UINTN   CpuIndex,
 701   IN UINT32  SmBase,
 702   IN VOID    *SmiStack,
 703   IN UINTN   StackSize,
 704   IN UINTN   GdtBase,
 705   IN UINTN   GdtSize,
 706   IN UINTN   IdtBase,
 707   IN UINTN   IdtSize,
 708   IN UINT32  Cr3
 709   );
 710
 711 /**
 712   Search module name by input IP address and output it.
 713
 714   @param CallerIpAddress   Caller instruction pointer.
 715
 716 **/
 717 VOID
 718 DumpModuleInfoByIp (
 719   IN  UINTN              CallerIpAddress
 720   );
 721
 722 /**
 723   This API provides a way to allocate memory for page table.
 724
 725   This API can be called more once to allocate memory for page tables.
 726
 727   Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
 728   allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
 729   is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
 730   returned.
 731
 732   @param  Pages                 The number of 4 KB pages to allocate.
 733
 734   @return A pointer to the allocated buffer or NULL if allocation fails.
 735
 736 **/
 737 VOID *
 738 AllocatePageTableMemory (
 739   IN UINTN           Pages
 740   );
 741
 742 #endif