UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h

   1 /** @file
   2 SMM profile internal header file.
   3
   4 Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _SMM_PROFILE_INTERNAL_H_
  16 #define _SMM_PROFILE_INTERNAL_H_
  17
  18 #include <Guid/GlobalVariable.h>
  19 #include <Guid/Acpi.h>
  20 #include <Protocol/SmmReadyToLock.h>
  21 #include <Library/UefiRuntimeServicesTableLib.h>
  22 #include <Library/DxeServicesTableLib.h>
  23 #include <Library/CpuLib.h>
  24 #include <IndustryStandard/Acpi.h>
  25
  26 #include "SmmProfileArch.h"
  27
  28 //
  29 // Configure the SMM_PROFILE DTS region size
  30 //
  31 #define SMM_PROFILE_DTS_SIZE       (4 * 1024 * 1024) // 4M
  32
  33 #define MAX_PF_PAGE_COUNT           0x2
  34
  35 #define PEBS_RECORD_NUMBER          0x2
  36
  37 #define MAX_PF_ENTRY_COUNT          10
  38
  39 //
  40 // This MACRO just enable unit test for the profile
  41 // Please disable it.
  42 //
  43
  44 #define IA32_PF_EC_ID               (1u << 4)
  45
  46 #define SMM_PROFILE_NAME            L"SmmProfileData"
  47
  48 //
  49 // CPU generic definition
  50 //
  51 #define   CPUID1_EDX_XD_SUPPORT      0x100000
  52 #define   MSR_EFER                   0xc0000080
  53 #define   MSR_EFER_XD                0x800
  54
  55 #define   CPUID1_EDX_BTS_AVAILABLE   0x200000
  56
  57 #define   DR6_SINGLE_STEP            0x4000
  58 #define   RFLAG_TF                   0x100
  59
  60 #define MSR_DEBUG_CTL                0x1D9
  61 #define   MSR_DEBUG_CTL_LBR          0x1
  62 #define   MSR_DEBUG_CTL_TR           0x40
  63 #define   MSR_DEBUG_CTL_BTS          0x80
  64 #define   MSR_DEBUG_CTL_BTINT        0x100
  65 #define MSR_DS_AREA                  0x600
  66
  67 typedef struct {
  68   EFI_PHYSICAL_ADDRESS   Base;
  69   EFI_PHYSICAL_ADDRESS   Top;
  70 } MEMORY_RANGE;
  71
  72 typedef struct {
  73   MEMORY_RANGE   Range;
  74   BOOLEAN        Present;
  75   BOOLEAN        Nx;
  76 } MEMORY_PROTECTION_RANGE;
  77
  78 typedef struct {
  79   UINT64  HeaderSize;
  80   UINT64  MaxDataEntries;
  81   UINT64  MaxDataSize;
  82   UINT64  CurDataEntries;
  83   UINT64  CurDataSize;
  84   UINT64  TsegStart;
  85   UINT64  TsegSize;
  86   UINT64  NumSmis;
  87   UINT64  NumCpus;
  88 } SMM_PROFILE_HEADER;
  89
  90 typedef struct {
  91   UINT64  SmiNum;
  92   UINT64  CpuNum;
  93   UINT64  ApicId;
  94   UINT64  ErrorCode;
  95   UINT64  Instruction;
  96   UINT64  Address;
  97   UINT64  SmiCmd;
  98 } SMM_PROFILE_ENTRY;
  99
 100 extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;
 101 extern UINTN                     gSmiExceptionHandlers[];
 102 extern BOOLEAN                   mXdSupported;
 103 extern UINTN                     *mPFEntryCount;
 104 extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
 105 extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
 106
 107 //
 108 // Internal functions
 109 //
 110
 111 /**
 112   Update IDT table to replace page fault handler and INT 1 handler.
 113
 114 **/
 115 VOID
 116 InitIdtr (
 117   VOID
 118   );
 119
 120 /**
 121   Check if the memory address will be mapped by 4KB-page.
 122
 123   @param  Address  The address of Memory.
 124
 125 **/
 126 BOOLEAN
 127 IsAddressSplit (
 128   IN EFI_PHYSICAL_ADDRESS   Address
 129   );
 130
 131 /**
 132   Check if the memory address will be mapped by 4KB-page.
 133
 134   @param  Address  The address of Memory.
 135   @param  Nx       The flag indicates if the memory is execute-disable.
 136
 137 **/
 138 BOOLEAN
 139 IsAddressValid (
 140   IN EFI_PHYSICAL_ADDRESS   Address,
 141   IN BOOLEAN                *Nx
 142   );
 143
 144 /**
 145   Page Fault handler for SMM use.
 146
 147 **/
 148 VOID
 149 SmiDefaultPFHandler (
 150   VOID
 151   );
 152
 153 /**
 154   Clear TF in FLAGS.
 155
 156   @param  SystemContext    A pointer to the processor context when
 157                            the interrupt occurred on the processor.
 158
 159 **/
 160 VOID
 161 ClearTrapFlag (
 162   IN OUT EFI_SYSTEM_CONTEXT   SystemContext
 163   );
 164
 165 #endif // _SMM_PROFILE_H_