1 #------------------------------------------------------------------------------
3 # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php.
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 # Exception handlers used in SM mode
20 #------------------------------------------------------------------------------
22 ASM_GLOBAL ASM_PFX(SmiPFHandler)
23 ASM_GLOBAL ASM_PFX(gSmiMtrrs)
24 ASM_GLOBAL ASM_PFX(gcSmiIdtr)
25 ASM_GLOBAL ASM_PFX(gcSmiGdtr)
26 ASM_GLOBAL ASM_PFX(gcPsd)
30 NullSeg: .quad 0 # reserved by architecture
36 .byte 0xcf # LimitHigh
43 .byte 0xcf # LimitHigh
50 .byte 0xcf # LimitHigh
57 .byte 0xcf # LimitHigh
78 .byte 0xaf # LimitHigh
80 # TSS Segment for X64 specially
82 .word TSS_DESC_SIZE - 1 # LimitLow
86 .byte 0x00 # LimitHigh
90 .equ GDT_SIZE, .- NullSeg
94 .equ TSS_DESC_SIZE, .- TssDescriptor
97 # This structure serves as a template for all processors.
111 .quad 0 # fixed in InitializeMpServiceData()
116 .quad ASM_PFX(gSmiMtrrs)
117 .equ PSD_SIZE, . - ASM_PFX(gcPsd)
120 # CODE & DATA segments for SMM runtime
122 .equ CODE_SEL, CodeSeg64 - NullSeg
123 .equ DATA_SEL, DataSeg32 - NullSeg
124 .equ CODE32_SEL, CodeSeg32 - NullSeg
136 #------------------------------------------------------------------------------
137 # _SmiExceptionEntryPoints is the collection of exception entry points followed
138 # by a common exception handler.
140 # Stack frame would be as follows as specified in IA32 manuals:
141 # +---------------------+ <-- 16-byte aligned ensured by processor
143 # +---------------------+
145 # +---------------------+
147 # +---------------------+
149 # +---------------------+
151 # +---------------------+
153 # +---------------------+
155 # +---------------------+
157 # +---------------------+ <-- RBP, 16-byte aligned
159 # RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
160 #------------------------------------------------------------------------------
161 ASM_GLOBAL ASM_PFX(PageFaultIdtHandlerSmmProfile)
162 ASM_PFX(PageFaultIdtHandlerSmmProfile):
163 pushq $0x0e # Page Fault
164 .byte 0x40, 0xf6, 0xc4, 0x08 #test spl, 8
173 # Since here the stack pointer is 16-byte aligned, so
174 # EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
178 ## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
179 ## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
197 ## UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
198 movzwq 56(%rbp), %rax
200 movzwq 32(%rbp), %rax
214 ## UINT64 Gdtr[2], Idtr[2];
230 ## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
246 ## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
260 ## FX_SAVE_STATE_X64 FxSaveState;
264 .byte 0xf, 0xae, 0x7 # fxsave [rdi]
266 # UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
269 ## UINT32 ExceptionData;
272 ## call into exception handler
274 movabsq $ASM_PFX(SmiPFHandler), %rax
276 ## Prepare parameter and call
279 # Per X64 calling convention, allocate maximum parameter stack space
280 # and make sure RSP is 16-byte aligned
282 subq $4 * 8 + 8, %rsp
284 addq $4 * 8 + 8, %rsp
288 ## UINT64 ExceptionData;
291 ## FX_SAVE_STATE_X64 FxSaveState;
294 .byte 0xf, 0xae, 0xe # fxrstor [rsi]
297 ## UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
298 ## Skip restoration of DRx registers to support debuggers
299 ## that set breakpoints in interrupt/exception context
302 ## UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
305 addq $8, %rsp # not for Cr1
319 ## UINT64 Gdtr[2], Idtr[2];
320 ## Best not let anyone mess with these particular registers...
326 ## UINT64 Gs, Fs, Es, Ds, Cs, Ss;
328 # mov gs, rax ; not for gs
330 # mov fs, rax ; not for fs
331 # (X64 will not use fs and gs, so we do not restore it)
336 popq 32(%rbp) # for cs
337 popq 56(%rbp) # for ss
339 ## UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
340 ## UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
343 addq $8, %rsp # not for rbp
344 popq 48(%rbp) # for rsp
360 # Enable TF bit after page fault handler runs
361 btsl $8, 40(%rsp) #RFLAGS
364 addq $16, %rsp # skip INT# & ErrCode