1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 EXTERNDEF SmiPFHandler:PROC
22 EXTERNDEF gSmiMtrrs:QWORD
23 EXTERNDEF gcSmiIdtr:FWORD
24 EXTERNDEF gcSmiGdtr:FWORD
29 NullSeg DQ 0 ; reserved by architecture
37 ProtModeCodeSeg32 LABEL QWORD
44 ProtModeSsSeg32 LABEL QWORD
79 ; TSS Segment for X64 specially
81 DW TSS_DESC_SIZE - 1 ; LimitLow
89 GDT_SIZE = $ - offset NullSeg
91 ; Create TSS Descriptor just after GDT
92 TssDescriptor LABEL BYTE
109 DW 0 ; I/O Map Base Address
110 TSS_DESC_SIZE = $ - offset TssDescriptor
113 ; This structure serves as a template for all processors.
127 DQ 0 ; fixed in InitializeMpServiceData()
133 PSD_SIZE = $ - offset gcPsd
136 ; CODE & DATA segments for SMM runtime
138 CODE_SEL = offset CodeSeg64 - offset NullSeg
139 DATA_SEL = offset DataSeg32 - offset NullSeg
140 CODE32_SEL = offset CodeSeg32 - offset NullSeg
142 gcSmiGdtr LABEL FWORD
146 gcSmiIdtr LABEL FWORD
152 ;------------------------------------------------------------------------------
153 ; _SmiExceptionEntryPoints is the collection of exception entry points followed
154 ; by a common exception handler.
156 ; Stack frame would be as follows as specified in IA32 manuals:
158 ; +---------------------+ <-- 16-byte aligned ensured by processor
160 ; +---------------------+
162 ; +---------------------+
164 ; +---------------------+
166 ; +---------------------+
168 ; +---------------------+
170 ; +---------------------+
172 ; +---------------------+
174 ; +---------------------+ <-- RBP, 16-byte aligned
176 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
177 ;------------------------------------------------------------------------------
178 PageFaultIdtHandlerSmmProfile PROC
179 push 0eh ; Page Fault
180 test spl, 8 ; odd multiple of 8 => ErrCode present
182 push [rsp] ; duplicate INT# if no ErrCode
183 mov qword ptr [rsp + 8], 0
189 ; Since here the stack pointer is 16-byte aligned, so
190 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
194 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
195 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
208 push qword ptr [rbp + 48] ; RSP
209 push qword ptr [rbp] ; RBP
213 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
214 movzx rax, word ptr [rbp + 56]
216 movzx rax, word ptr [rbp + 32]
228 push qword ptr [rbp + 24]
230 ;; UINT64 Gdtr[2], Idtr[2];
244 push qword ptr [rbp + 40]
246 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
262 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
276 ;; FX_SAVE_STATE_X64 FxSaveState;
280 db 0fh, 0aeh, 00000111y ;fxsave [rdi]
282 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
285 ;; UINT32 ExceptionData;
286 push qword ptr [rbp + 16]
288 ;; call into exception handler
290 mov rax, SmiPFHandler
292 ;; Prepare parameter and call
295 ; Per X64 calling convention, allocate maximum parameter stack space
296 ; and make sure RSP is 16-byte aligned
304 ;; UINT64 ExceptionData;
307 ;; FX_SAVE_STATE_X64 FxSaveState;
310 db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
313 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
314 ;; Skip restoration of DRx registers to support debuggers
315 ;; that set breakpoints in interrupt/exception context
318 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
321 add rsp, 8 ; not for Cr1
332 pop qword ptr [rbp + 40]
335 ;; UINT64 Gdtr[2], Idtr[2];
336 ;; Best not let anyone mess with these particular registers...
340 pop qword ptr [rbp + 24]
342 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
344 ; mov gs, rax ; not for gs
346 ; mov fs, rax ; not for fs
347 ; (X64 will not use fs and gs, so we do not restore it)
352 pop qword ptr [rbp + 32] ; for cs
353 pop qword ptr [rbp + 56] ; for ss
355 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
356 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
359 add rsp, 8 ; not for rbp
360 pop qword ptr [rbp + 48] ; for rsp
376 ; Enable TF bit after page fault handler runs
377 bts dword ptr [rsp + 40], 8 ;RFLAGS
380 add rsp, 16 ; skip INT# & ErrCode
382 PageFaultIdtHandlerSmmProfile ENDP