1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 extern ASM_PFX(SmiPFHandler)
22 extern ASM_PFX(gSmiMtrrs)
24 global ASM_PFX(gcSmiIdtr)
25 global ASM_PFX(gcSmiGdtr)
30 NullSeg: DQ 0 ; reserved by architecture
80 ; TSS Segment for X64 specially
82 DW TSS_DESC_SIZE ; LimitLow
90 GDT_SIZE equ $ - NullSeg
92 ; Create TSS Descriptor just after GDT
110 DW 0 ; I/O Map Base Address
111 TSS_DESC_SIZE equ $ - TssDescriptor
114 ; This structure serves as a template for all processors.
128 DQ 0 ; fixed in InitializeMpServiceData()
133 DQ ASM_PFX(gSmiMtrrs)
134 PSD_SIZE equ $ - ASM_PFX(gcPsd)
137 ; CODE & DATA segments for SMM runtime
139 CODE_SEL equ CodeSeg64 - NullSeg
140 DATA_SEL equ DataSeg32 - NullSeg
141 CODE32_SEL equ CodeSeg32 - NullSeg
154 ;------------------------------------------------------------------------------
155 ; _SmiExceptionEntryPoints is the collection of exception entrypoints followed
156 ; by a common exception handler.
158 ; Stack frame would be as follows as specified in IA32 manuals:
160 ; +---------------------+ <-- 16-byte aligned ensured by processor
162 ; +---------------------+
164 ; +---------------------+
166 ; +---------------------+
168 ; +---------------------+
170 ; +---------------------+
172 ; +---------------------+
174 ; +---------------------+
176 ; +---------------------+ <-- RBP, 16-byte aligned
178 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
179 ;------------------------------------------------------------------------------
180 global ASM_PFX(PageFaultIdtHandlerSmmProfile)
181 ASM_PFX(PageFaultIdtHandlerSmmProfile):
182 push 0xe ; Page Fault
183 test spl, 8 ; odd multiple of 8 => ErrCode present
185 push qword [rsp] ; duplicate INT# if no ErrCode
186 mov qword [rsp + 8], 0
192 ; Since here the stack pointer is 16-byte aligned, so
193 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
197 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
198 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
211 push qword [rbp + 48] ; RSP
212 push qword [rbp] ; RBP
216 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
217 movzx rax, word [rbp + 56]
219 movzx rax, word [rbp + 32]
231 push qword [rbp + 24]
233 ;; UINT64 Gdtr[2], Idtr[2];
247 push qword [rbp + 40]
249 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
265 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
279 ;; FX_SAVE_STATE_X64 FxSaveState;
283 db 0xf, 0xae, 00000111y ;fxsave [rdi]
285 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
288 ;; UINT32 ExceptionData;
289 push qword [rbp + 16]
291 ;; call into exception handler
293 mov rax, ASM_PFX(SmiPFHandler)
295 ;; Prepare parameter and call
298 ; Per X64 calling convention, allocate maximum parameter stack space
299 ; and make sure RSP is 16-byte aligned
307 ;; UINT64 ExceptionData;
310 ;; FX_SAVE_STATE_X64 FxSaveState;
313 db 0xf, 0xae, 00001110y ; fxrstor [rsi]
316 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
317 ;; Skip restoration of DRx registers to support debuggers
318 ;; that set breakpoints in interrupt/exception context
321 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
324 add rsp, 8 ; not for Cr1
338 ;; UINT64 Gdtr[2], Idtr[2];
339 ;; Best not let anyone mess with these particular registers...
345 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
347 ; mov gs, rax ; not for gs
349 ; mov fs, rax ; not for fs
350 ; (X64 will not use fs and gs, so we do not restore it)
355 pop qword [rbp + 32] ; for cs
356 pop qword [rbp + 56] ; for ss
358 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
359 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
362 add rsp, 8 ; not for rbp
363 pop qword [rbp + 48] ; for rsp
379 ; Enable TF bit after page fault handler runs
380 bts dword [rsp + 40], 8 ;RFLAGS
383 add rsp, 16 ; skip INT# & ErrCode