UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmmInit.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Functions for relocating SMBASE's for all processors
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 extern ASM_PFX(SmmInitHandler)
  22 extern ASM_PFX(mRebasedFlag)
  23 extern ASM_PFX(mSmmRelocationOriginalAddress)
  24
  25 global ASM_PFX(gPatchSmmCr3)
  26 global ASM_PFX(gPatchSmmCr4)
  27 global ASM_PFX(gPatchSmmCr0)
  28 global ASM_PFX(gPatchSmmInitStack)
  29 global ASM_PFX(gcSmiInitGdtr)
  30 global ASM_PFX(gcSmmInitSize)
  31 global ASM_PFX(gcSmmInitTemplate)
  32 global ASM_PFX(gPatchRebasedFlagAddr32)
  33 global ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32)
  34
  35 %define LONG_MODE_CS 0x38
  36
  37     DEFAULT REL
  38     SECTION .text
  39
  40 ASM_PFX(gcSmiInitGdtr):
  41             DW      0
  42             DQ      0
  43
  44 global ASM_PFX(SmmStartup)
  45
  46 BITS 16
  47 ASM_PFX(SmmStartup):
  48     mov     eax, 0x80000001             ; read capability
  49     cpuid
  50     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  51     mov     eax, strict dword 0         ; source operand will be patched
  52 ASM_PFX(gPatchSmmCr3):
  53     mov     cr3, eax
  54 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  55     mov     eax, strict dword 0         ; source operand will be patched
  56 ASM_PFX(gPatchSmmCr4):
  57     or      ah,  2                      ; enable XMM registers access
  58     mov     cr4, eax
  59     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  60     rdmsr
  61     or      ah, BIT0                    ; set LME bit
  62     test    ebx, BIT20                  ; check NXE capability
  63     jz      .1
  64     or      ah, BIT3                    ; set NXE bit
  65 .1:
  66     wrmsr
  67     mov     eax, strict dword 0         ; source operand will be patched
  68 ASM_PFX(gPatchSmmCr0):
  69     mov     cr0, eax                    ; enable protected mode & paging
  70     jmp     LONG_MODE_CS : dword 0      ; offset will be patched to @LongMode
  71 @PatchLongModeOffset:
  72
  73 BITS 64
  74 @LongMode:                              ; long-mode starts here
  75     mov     rsp, strict qword 0         ; source operand will be patched
  76 ASM_PFX(gPatchSmmInitStack):
  77     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
  78     ;
  79     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
  80     ; them before calling C-function.
  81     ;
  82     sub     rsp, 0x60
  83     movdqa  [rsp], xmm0
  84     movdqa  [rsp + 0x10], xmm1
  85     movdqa  [rsp + 0x20], xmm2
  86     movdqa  [rsp + 0x30], xmm3
  87     movdqa  [rsp + 0x40], xmm4
  88     movdqa  [rsp + 0x50], xmm5
  89
  90     add     rsp, -0x20
  91     call    ASM_PFX(SmmInitHandler)
  92     add     rsp, 0x20
  93
  94     ;
  95     ; Restore XMM0~5 after calling C-function.
  96     ;
  97     movdqa  xmm0, [rsp]
  98     movdqa  xmm1, [rsp + 0x10]
  99     movdqa  xmm2, [rsp + 0x20]
 100     movdqa  xmm3, [rsp + 0x30]
 101     movdqa  xmm4, [rsp + 0x40]
 102     movdqa  xmm5, [rsp + 0x50]
 103
 104     rsm
 105
 106 BITS 16
 107 ASM_PFX(gcSmmInitTemplate):
 108     mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
 109     sub ebp, 0x30000
 110     jmp ebp
 111 @L1:
 112     DQ     0; ASM_PFX(SmmStartup)
 113
 114 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
 115
 116 BITS 64
 117 global ASM_PFX(SmmRelocationSemaphoreComplete)
 118 ASM_PFX(SmmRelocationSemaphoreComplete):
 119     push    rax
 120     mov     rax, [ASM_PFX(mRebasedFlag)]
 121     mov     byte [rax], 1
 122     pop     rax
 123     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
 124
 125 ;
 126 ; Semaphore code running in 32-bit mode
 127 ;
 128 BITS 32
 129 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 130 ASM_PFX(SmmRelocationSemaphoreComplete32):
 131     push    eax
 132     mov     eax, strict dword 0                ; source operand will be patched
 133 ASM_PFX(gPatchRebasedFlagAddr32):
 134     mov     byte [eax], 1
 135     pop     eax
 136     jmp     dword [dword 0]                    ; destination will be patched
 137 ASM_PFX(gPatchSmmRelocationOriginalAddressPtr32):
 138
 139 BITS 64
 140 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 141 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 142     lea    rax, [@LongMode]
 143     lea    rcx, [@PatchLongModeOffset - 6]
 144     mov    dword [rcx], eax
 145
 146     lea    rax, [ASM_PFX(SmmStartup)]
 147     lea    rcx, [@L1]
 148     mov    qword [rcx], rax
 149     ret