1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Functions for relocating SMBASE's for all processors
19 ;-------------------------------------------------------------------------------
21 extern ASM_PFX(SmmInitHandler)
22 extern ASM_PFX(mRebasedFlag)
23 extern ASM_PFX(mSmmRelocationOriginalAddress)
25 global ASM_PFX(gPatchSmmCr3)
26 global ASM_PFX(gPatchSmmCr4)
27 global ASM_PFX(gPatchSmmCr0)
28 global ASM_PFX(gSmmJmpAddr)
29 global ASM_PFX(gSmmInitStack)
30 global ASM_PFX(gcSmiInitGdtr)
31 global ASM_PFX(gcSmmInitSize)
32 global ASM_PFX(gcSmmInitTemplate)
33 global ASM_PFX(mRebasedFlagAddr32)
34 global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
39 ASM_PFX(gcSmiInitGdtr):
43 global ASM_PFX(SmmStartup)
47 mov eax, 0x80000001 ; read capability
49 mov ebx, edx ; rdmsr will change edx. keep it in ebx.
50 mov eax, strict dword 0 ; source operand will be patched
51 ASM_PFX(gPatchSmmCr3):
53 o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
54 mov eax, strict dword 0 ; source operand will be patched
55 ASM_PFX(gPatchSmmCr4):
56 or ah, 2 ; enable XMM registers access
58 mov ecx, 0xc0000080 ; IA32_EFER MSR
60 or ah, BIT0 ; set LME bit
61 test ebx, BIT20 ; check NXE capability
63 or ah, BIT3 ; set NXE bit
66 mov eax, strict dword 0 ; source operand will be patched
67 ASM_PFX(gPatchSmmCr0):
68 mov cr0, eax ; enable protected mode & paging
69 DB 0x66, 0xea ; far jmp to long mode
70 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
73 @LongMode: ; long-mode starts here
74 DB 0x48, 0xbc ; mov rsp, imm64
75 ASM_PFX(gSmmInitStack): DQ 0
76 and sp, 0xfff0 ; make sure RSP is 16-byte aligned
78 ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
79 ; them before calling C-function.
83 movdqa [rsp + 0x10], xmm1
84 movdqa [rsp + 0x20], xmm2
85 movdqa [rsp + 0x30], xmm3
86 movdqa [rsp + 0x40], xmm4
87 movdqa [rsp + 0x50], xmm5
90 call ASM_PFX(SmmInitHandler)
94 ; Restore XMM0~5 after calling C-function.
97 movdqa xmm1, [rsp + 0x10]
98 movdqa xmm2, [rsp + 0x20]
99 movdqa xmm3, [rsp + 0x30]
100 movdqa xmm4, [rsp + 0x40]
101 movdqa xmm5, [rsp + 0x50]
106 ASM_PFX(gcSmmInitTemplate):
107 mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
111 DQ 0; ASM_PFX(SmmStartup)
113 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
116 global ASM_PFX(SmmRelocationSemaphoreComplete)
117 ASM_PFX(SmmRelocationSemaphoreComplete):
119 mov rax, [ASM_PFX(mRebasedFlag)]
122 jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
125 ; Semaphore code running in 32-bit mode
127 global ASM_PFX(SmmRelocationSemaphoreComplete32)
128 ASM_PFX(SmmRelocationSemaphoreComplete32):
133 ASM_PFX(mRebasedFlagAddr32): dd 0
139 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
141 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
142 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
144 lea rcx, [ASM_PFX(gSmmJmpAddr)]
147 lea rax, [ASM_PFX(SmmStartup)]