UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmmInit.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Functions for relocating SMBASE's for all processors
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 extern ASM_PFX(SmmInitHandler)
  22 extern ASM_PFX(mRebasedFlag)
  23 extern ASM_PFX(mSmmRelocationOriginalAddress)
  24
  25 global ASM_PFX(gSmmCr3)
  26 global ASM_PFX(gSmmCr4)
  27 global ASM_PFX(gSmmCr0)
  28 global ASM_PFX(gSmmJmpAddr)
  29 global ASM_PFX(gSmmInitStack)
  30 global ASM_PFX(gcSmiInitGdtr)
  31 global ASM_PFX(gcSmmInitSize)
  32 global ASM_PFX(gcSmmInitTemplate)
  33 global ASM_PFX(mRebasedFlagAddr32)
  34 global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
  35
  36     DEFAULT REL
  37     SECTION .text
  38
  39 ASM_PFX(gcSmiInitGdtr):
  40             DW      0
  41             DQ      0
  42
  43 global ASM_PFX(SmmStartup)
  44 ASM_PFX(SmmStartup):
  45     DB      0x66
  46     mov     eax, 0x80000001             ; read capability
  47     cpuid
  48     DB      0x66
  49     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  50     DB      0x66, 0xb8                   ; mov eax, imm32
  51 ASM_PFX(gSmmCr3): DD 0
  52     mov     cr3, rax
  53     DB      0x66, 0x2e
  54     lgdt    [ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  55     DB      0x66, 0xb8                   ; mov eax, imm32
  56 ASM_PFX(gSmmCr4): DD 0
  57     or      ah,  2                      ; enable XMM registers access
  58     mov     cr4, rax
  59     DB      0x66
  60     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  61     rdmsr
  62     or      ah, BIT0                    ; set LME bit
  63     DB      0x66
  64     test    ebx, BIT20                  ; check NXE capability
  65     jz      .1
  66     or      ah, BIT3                    ; set NXE bit
  67 .1:
  68     wrmsr
  69     DB      0x66, 0xb8                   ; mov eax, imm32
  70 ASM_PFX(gSmmCr0): DD 0
  71     mov     cr0, rax                    ; enable protected mode & paging
  72     DB      0x66, 0xea                   ; far jmp to long mode
  73 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
  74 @LongMode:                              ; long-mode starts here
  75     DB      0x48, 0xbc                   ; mov rsp, imm64
  76 ASM_PFX(gSmmInitStack): DQ 0
  77     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
  78     ;
  79     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
  80     ; them before calling C-function.
  81     ;
  82     sub     rsp, 0x60
  83     movdqa  [rsp], xmm0
  84     movdqa  [rsp + 0x10], xmm1
  85     movdqa  [rsp + 0x20], xmm2
  86     movdqa  [rsp + 0x30], xmm3
  87     movdqa  [rsp + 0x40], xmm4
  88     movdqa  [rsp + 0x50], xmm5
  89
  90     add     rsp, -0x20
  91     call    ASM_PFX(SmmInitHandler)
  92     add     rsp, 0x20
  93
  94     ;
  95     ; Restore XMM0~5 after calling C-function.
  96     ;
  97     movdqa  xmm0, [rsp]
  98     movdqa  xmm1, [rsp + 0x10]
  99     movdqa  xmm2, [rsp + 0x20]
 100     movdqa  xmm3, [rsp + 0x30]
 101     movdqa  xmm4, [rsp + 0x40]
 102     movdqa  xmm5, [rsp + 0x50]
 103
 104     rsm
 105
 106 BITS 16
 107 ASM_PFX(gcSmmInitTemplate):
 108     mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
 109     sub ebp, 0x30000
 110     jmp ebp
 111 @L1:
 112     DQ     0; ASM_PFX(SmmStartup)
 113
 114 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
 115
 116 BITS 64
 117 global ASM_PFX(SmmRelocationSemaphoreComplete)
 118 ASM_PFX(SmmRelocationSemaphoreComplete):
 119     push    rax
 120     mov     rax, [ASM_PFX(mRebasedFlag)]
 121     mov     byte [rax], 1
 122     pop     rax
 123     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
 124
 125 ;
 126 ; Semaphore code running in 32-bit mode
 127 ;
 128 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 129 ASM_PFX(SmmRelocationSemaphoreComplete32):
 130     ;
 131     ; mov byte ptr [], 1
 132     ;
 133     db      0xc6, 0x5
 134 ASM_PFX(mRebasedFlagAddr32): dd 0
 135     db      1
 136     ;
 137     ; jmp dword ptr []
 138     ;
 139     db      0xff, 0x25
 140 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
 141
 142 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 143 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 144     lea    rax, [@LongMode]
 145     lea    rcx, [ASM_PFX(gSmmJmpAddr)]
 146     mov    qword [rcx], rax
 147
 148     lea    rax, [ASM_PFX(SmmStartup)]
 149     lea    rcx, [@L1]
 150     mov    qword [rcx], rax
 151     ret