UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm

   1 ;------------------------------------------------------------------------------ ;
   2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
   3 ; This program and the accompanying materials
   4 ; are licensed and made available under the terms and conditions of the BSD License
   5 ; which accompanies this distribution.  The full text of the license may be found at
   6 ; http://opensource.org/licenses/bsd-license.php.
   7 ;
   8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10 ;
  11 ; Module Name:
  12 ;
  13 ;   SmmInit.nasm
  14 ;
  15 ; Abstract:
  16 ;
  17 ;   Functions for relocating SMBASE's for all processors
  18 ;
  19 ;-------------------------------------------------------------------------------
  20
  21 extern ASM_PFX(SmmInitHandler)
  22 extern ASM_PFX(mRebasedFlag)
  23 extern ASM_PFX(mSmmRelocationOriginalAddress)
  24
  25 global ASM_PFX(gSmmCr3)
  26 global ASM_PFX(gSmmCr4)
  27 global ASM_PFX(gSmmCr0)
  28 global ASM_PFX(gSmmJmpAddr)
  29 global ASM_PFX(gSmmInitStack)
  30 global ASM_PFX(gcSmiInitGdtr)
  31 global ASM_PFX(gcSmmInitSize)
  32 global ASM_PFX(gcSmmInitTemplate)
  33 global ASM_PFX(mRebasedFlagAddr32)
  34 global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
  35
  36     DEFAULT REL
  37     SECTION .text
  38
  39 ASM_PFX(gcSmiInitGdtr):
  40             DW      0
  41             DQ      0
  42
  43 global ASM_PFX(SmmStartup)
  44
  45 BITS 16
  46 ASM_PFX(SmmStartup):
  47     mov     eax, 0x80000001             ; read capability
  48     cpuid
  49     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.
  50     DB      0x66, 0xb8                   ; mov eax, imm32
  51 ASM_PFX(gSmmCr3): DD 0
  52     mov     cr3, eax
  53 o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]
  54     DB      0x66, 0xb8                   ; mov eax, imm32
  55 ASM_PFX(gSmmCr4): DD 0
  56     or      ah,  2                      ; enable XMM registers access
  57     mov     cr4, eax
  58     mov     ecx, 0xc0000080             ; IA32_EFER MSR
  59     rdmsr
  60     or      ah, BIT0                    ; set LME bit
  61     test    ebx, BIT20                  ; check NXE capability
  62     jz      .1
  63     or      ah, BIT3                    ; set NXE bit
  64 .1:
  65     wrmsr
  66     DB      0x66, 0xb8                   ; mov eax, imm32
  67 ASM_PFX(gSmmCr0): DD 0
  68     mov     cr0, eax                    ; enable protected mode & paging
  69     DB      0x66, 0xea                   ; far jmp to long mode
  70 ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
  71
  72 BITS 64
  73 @LongMode:                              ; long-mode starts here
  74     DB      0x48, 0xbc                   ; mov rsp, imm64
  75 ASM_PFX(gSmmInitStack): DQ 0
  76     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned
  77     ;
  78     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
  79     ; them before calling C-function.
  80     ;
  81     sub     rsp, 0x60
  82     movdqa  [rsp], xmm0
  83     movdqa  [rsp + 0x10], xmm1
  84     movdqa  [rsp + 0x20], xmm2
  85     movdqa  [rsp + 0x30], xmm3
  86     movdqa  [rsp + 0x40], xmm4
  87     movdqa  [rsp + 0x50], xmm5
  88
  89     add     rsp, -0x20
  90     call    ASM_PFX(SmmInitHandler)
  91     add     rsp, 0x20
  92
  93     ;
  94     ; Restore XMM0~5 after calling C-function.
  95     ;
  96     movdqa  xmm0, [rsp]
  97     movdqa  xmm1, [rsp + 0x10]
  98     movdqa  xmm2, [rsp + 0x20]
  99     movdqa  xmm3, [rsp + 0x30]
 100     movdqa  xmm4, [rsp + 0x40]
 101     movdqa  xmm5, [rsp + 0x50]
 102
 103     rsm
 104
 105 BITS 16
 106 ASM_PFX(gcSmmInitTemplate):
 107     mov ebp, [cs:@L1 - ASM_PFX(gcSmmInitTemplate) + 0x8000]
 108     sub ebp, 0x30000
 109     jmp ebp
 110 @L1:
 111     DQ     0; ASM_PFX(SmmStartup)
 112
 113 ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
 114
 115 BITS 64
 116 global ASM_PFX(SmmRelocationSemaphoreComplete)
 117 ASM_PFX(SmmRelocationSemaphoreComplete):
 118     push    rax
 119     mov     rax, [ASM_PFX(mRebasedFlag)]
 120     mov     byte [rax], 1
 121     pop     rax
 122     jmp     [ASM_PFX(mSmmRelocationOriginalAddress)]
 123
 124 ;
 125 ; Semaphore code running in 32-bit mode
 126 ;
 127 global ASM_PFX(SmmRelocationSemaphoreComplete32)
 128 ASM_PFX(SmmRelocationSemaphoreComplete32):
 129     ;
 130     ; mov byte ptr [], 1
 131     ;
 132     db      0xc6, 0x5
 133 ASM_PFX(mRebasedFlagAddr32): dd 0
 134     db      1
 135     ;
 136     ; jmp dword ptr []
 137     ;
 138     db      0xff, 0x25
 139 ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
 140
 141 global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
 142 ASM_PFX(PiSmmCpuSmmInitFixupAddress):
 143     lea    rax, [@LongMode]
 144     lea    rcx, [ASM_PFX(gSmmJmpAddr)]
 145     mov    qword [rcx], rax
 146
 147     lea    rax, [ASM_PFX(SmmStartup)]
 148     lea    rcx, [@L1]
 149     mov    qword [rcx], rax
 150     ret