UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c

   1 /** @file
   2 X64 processor specific functions to enable SMM profile.
   3
   4 Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
   5 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
   6
   7 This program and the accompanying materials
   8 are licensed and made available under the terms and conditions of the BSD License
   9 which accompanies this distribution.  The full text of the license may be found at
  10 http://opensource.org/licenses/bsd-license.php
  11
  12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15 **/
  16
  17 #include "PiSmmCpuDxeSmm.h"
  18 #include "SmmProfileInternal.h"
  19
  20 //
  21 // Current page index.
  22 //
  23 UINTN                     mPFPageIndex;
  24
  25 //
  26 // Pool for dynamically creating page table in page fault handler.
  27 //
  28 UINT64                    mPFPageBuffer;
  29
  30 //
  31 // Store the uplink information for each page being used.
  32 //
  33 UINT64                    *mPFPageUplink[MAX_PF_PAGE_COUNT];
  34
  35 /**
  36   Create SMM page table for S3 path.
  37
  38 **/
  39 VOID
  40 InitSmmS3Cr3 (
  41   VOID
  42   )
  43 {
  44   EFI_PHYSICAL_ADDRESS              Pages;
  45   UINT64                            *PTEntry;
  46
  47   //
  48   // Generate PAE page table for the first 4GB memory space
  49   //
  50   Pages = Gen4GPageTable (FALSE);
  51
  52   //
  53   // Fill Page-Table-Level4 (PML4) entry
  54   //
  55   PTEntry = (UINT64*)AllocatePageTableMemory (1);
  56   ASSERT (PTEntry != NULL);
  57   *PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
  58   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));
  59
  60   //
  61   // Return the address of PML4 (to set CR3)
  62   //
  63   mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;
  64
  65   return ;
  66 }
  67
  68 /**
  69   Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.
  70
  71 **/
  72 VOID
  73 InitPagesForPFHandler (
  74   VOID
  75   )
  76 {
  77   VOID          *Address;
  78
  79   //
  80   // Pre-Allocate memory for page fault handler
  81   //
  82   Address = NULL;
  83   Address = AllocatePages (MAX_PF_PAGE_COUNT);
  84   ASSERT (Address != NULL);
  85
  86   mPFPageBuffer =  (UINT64)(UINTN) Address;
  87   mPFPageIndex = 0;
  88   ZeroMem ((VOID *) (UINTN) mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);
  89   ZeroMem (mPFPageUplink, sizeof (mPFPageUplink));
  90
  91   return;
  92 }
  93
  94 /**
  95   Allocate one page for creating 4KB-page based on 2MB-page.
  96
  97   @param  Uplink   The address of Page-Directory entry.
  98
  99 **/
 100 VOID
 101 AcquirePage (
 102   UINT64          *Uplink
 103   )
 104 {
 105   UINT64          Address;
 106
 107   //
 108   // Get the buffer
 109   //
 110   Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex);
 111   ZeroMem ((VOID *) (UINTN) Address, EFI_PAGE_SIZE);
 112
 113   //
 114   // Cut the previous uplink if it exists and wasn't overwritten
 115   //
 116   if ((mPFPageUplink[mPFPageIndex] != NULL) && ((*mPFPageUplink[mPFPageIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK) == Address)) {
 117     *mPFPageUplink[mPFPageIndex] = 0;
 118   }
 119
 120   //
 121   // Link & Record the current uplink
 122   //
 123   *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
 124   mPFPageUplink[mPFPageIndex] = Uplink;
 125
 126   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;
 127 }
 128
 129 /**
 130   Update page table to map the memory correctly in order to make the instruction
 131   which caused page fault execute successfully. And it also save the original page
 132   table to be restored in single-step exception.
 133
 134   @param  PageTable           PageTable Address.
 135   @param  PFAddress           The memory address which caused page fault exception.
 136   @param  CpuIndex            The index of the processor.
 137   @param  ErrorCode           The Error code of exception.
 138   @param  IsValidPFAddress    The flag indicates if SMM profile data need be added.
 139
 140 **/
 141 VOID
 142 RestorePageTableAbove4G (
 143   UINT64        *PageTable,
 144   UINT64        PFAddress,
 145   UINTN         CpuIndex,
 146   UINTN         ErrorCode,
 147   BOOLEAN       *IsValidPFAddress
 148   )
 149 {
 150   UINTN         PTIndex;
 151   UINT64        Address;
 152   BOOLEAN       Nx;
 153   BOOLEAN       Existed;
 154   UINTN         Index;
 155   UINTN         PFIndex;
 156
 157   ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));
 158
 159   //
 160   // If page fault address is 4GB above.
 161   //
 162
 163   //
 164   // Check if page fault address has existed in page table.
 165   // If it exists in page table but page fault is generated,
 166   // there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.
 167   //
 168   Existed = FALSE;
 169   PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
 170   PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 171   if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
 172     // PML4E
 173     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 174     PTIndex = BitFieldRead64 (PFAddress, 30, 38);
 175     if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
 176       // PDPTE
 177       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 178       PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 179       // PD
 180       if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {
 181         //
 182         // 2MB page
 183         //
 184         Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 185         if ((Address & ~((1ull << 21) - 1)) == ((PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 21) - 1)))) {
 186           Existed = TRUE;
 187         }
 188       } else {
 189         //
 190         // 4KB page
 191         //
 192         PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);
 193         if (PageTable != 0) {
 194           //
 195           // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.
 196           //
 197           PTIndex = BitFieldRead64 (PFAddress, 12, 20);
 198           Address = (UINT64)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 199           if ((Address & ~((1ull << 12) - 1)) == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
 200             Existed = TRUE;
 201           }
 202         }
 203       }
 204     }
 205   }
 206
 207   //
 208   // If page entry does not existed in page table at all, create a new entry.
 209   //
 210   if (!Existed) {
 211
 212     if (IsAddressValid (PFAddress, &Nx)) {
 213       //
 214       // If page fault address above 4GB is in protected range but it causes a page fault exception,
 215       // Will create a page entry for this page fault address, make page table entry as present/rw and execution-disable.
 216       // this access is not saved into SMM profile data.
 217       //
 218       *IsValidPFAddress = TRUE;
 219     }
 220
 221     //
 222     // Create one entry in page table for page fault address.
 223     //
 224     SmiDefaultPFHandler ();
 225     //
 226     // Find the page table entry created just now.
 227     //
 228     PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);
 229     PFAddress = AsmReadCr2 ();
 230     // PML4E
 231     PTIndex = BitFieldRead64 (PFAddress, 39, 47);
 232     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 233     // PDPTE
 234     PTIndex = BitFieldRead64 (PFAddress, 30, 38);
 235     PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 236     // PD
 237     PTIndex = BitFieldRead64 (PFAddress, 21, 29);
 238     Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;
 239     //
 240     // Check if 2MB-page entry need be changed to 4KB-page entry.
 241     //
 242     if (IsAddressSplit (Address)) {
 243       AcquirePage (&PageTable[PTIndex]);
 244
 245       // PTE
 246       PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
 247       for (Index = 0; Index < 512; Index++) {
 248         PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
 249         if (!IsAddressValid (Address, &Nx)) {
 250           PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
 251         }
 252         if (Nx && mXdSupported) {
 253           PageTable[Index] = PageTable[Index] | IA32_PG_NX;
 254         }
 255         if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
 256           PTIndex = Index;
 257         }
 258         Address += SIZE_4KB;
 259       } // end for PT
 260     } else {
 261       //
 262       // Update 2MB page entry.
 263       //
 264       if (!IsAddressValid (Address, &Nx)) {
 265         //
 266         // Patch to remove present flag and rw flag.
 267         //
 268         PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
 269       }
 270       //
 271       // Set XD bit to 1
 272       //
 273       if (Nx && mXdSupported) {
 274         PageTable[PTIndex] = PageTable[PTIndex] | IA32_PG_NX;
 275       }
 276     }
 277   }
 278
 279   //
 280   // Record old entries with non-present status
 281   // Old entries include the memory which instruction is at and the memory which instruction access.
 282   //
 283   //
 284   ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);
 285   if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {
 286     PFIndex = mPFEntryCount[CpuIndex];
 287     mLastPFEntryValue[CpuIndex][PFIndex]   = PageTable[PTIndex];
 288     mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];
 289     mPFEntryCount[CpuIndex]++;
 290   }
 291
 292   //
 293   // Add present flag or clear XD flag to make page fault handler succeed.
 294   //
 295   PageTable[PTIndex] |= (UINT64)(PAGE_ATTRIBUTE_BITS);
 296   if ((ErrorCode & IA32_PF_EC_ID) != 0) {
 297     //
 298     // If page fault is caused by instruction fetch, clear XD bit in the entry.
 299     //
 300     PageTable[PTIndex] &= ~IA32_PG_NX;
 301   }
 302
 303   return;
 304 }
 305
 306 /**
 307   Clear TF in FLAGS.
 308
 309   @param  SystemContext    A pointer to the processor context when
 310                            the interrupt occurred on the processor.
 311
 312 **/
 313 VOID
 314 ClearTrapFlag (
 315   IN OUT EFI_SYSTEM_CONTEXT   SystemContext
 316   )
 317 {
 318   SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8;
 319 }