UefiCpuPkg/ResetVector/Vtf0/SerialDebug.asm

   1 ;------------------------------------------------------------------------------
   2 ; @file
   3 ; Serial port debug support macros
   4 ;
   5 ; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
   6 ; SPDX-License-Identifier: BSD-2-Clause-Patent
   7 ;
   8 ;------------------------------------------------------------------------------
   9
  10 ;//---------------------------------------------
  11 ;// UART Register Offsets
  12 ;//---------------------------------------------
  13 %define BAUD_LOW_OFFSET         0x00
  14 %define BAUD_HIGH_OFFSET        0x01
  15 %define IER_OFFSET              0x01
  16 %define LCR_SHADOW_OFFSET       0x01
  17 %define FCR_SHADOW_OFFSET       0x02
  18 %define IR_CONTROL_OFFSET       0x02
  19 %define FCR_OFFSET              0x02
  20 %define EIR_OFFSET              0x02
  21 %define BSR_OFFSET              0x03
  22 %define LCR_OFFSET              0x03
  23 %define MCR_OFFSET              0x04
  24 %define LSR_OFFSET              0x05
  25 %define MSR_OFFSET              0x06
  26
  27 ;//---------------------------------------------
  28 ;// UART Register Bit Defines
  29 ;//---------------------------------------------
  30 %define LSR_TXRDY               0x20
  31 %define LSR_RXDA                0x01
  32 %define DLAB                    0x01
  33
  34 ; UINT16  gComBase = 0x3f8;
  35 ; UINTN   gBps = 115200;
  36 ; UINT8   gData = 8;
  37 ; UINT8   gStop = 1;
  38 ; UINT8   gParity = 0;
  39 ; UINT8   gBreakSet = 0;
  40
  41 %define DEFAULT_COM_BASE 0x3f8
  42 %define DEFAULT_BPS 115200
  43 %define DEFAULT_DATA 8
  44 %define DEFAULT_STOP 1
  45 %define DEFAULT_PARITY 0
  46 %define DEFAULT_BREAK_SET 0
  47
  48 %define SERIAL_DEFAULT_LCR ( \
  49      (DEFAULT_BREAK_SET << 6) | \
  50      (DEFAULT_PARITY << 3) | \
  51      (DEFAULT_STOP << 2) | \
  52      (DEFAULT_DATA - 5) \
  53     )
  54
  55 %define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE
  56
  57 %macro  inFromSerialPort 1
  58     mov     dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)
  59     in      al, dx
  60 %endmacro
  61
  62 %macro  waitForSerialTxReady 0
  63
  64 %%waitingForTx:
  65     inFromSerialPort LSR_OFFSET
  66     test    al, LSR_TXRDY
  67     jz      %%waitingForTx
  68
  69 %endmacro
  70
  71 %macro  outToSerialPort 2
  72     mov     dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)
  73     mov     al, %2
  74     out     dx, al
  75 %endmacro
  76
  77 %macro  debugShowCharacter 1
  78     waitForSerialTxReady
  79     outToSerialPort 0, %1
  80 %endmacro
  81
  82 %macro  debugShowHexDigit 1
  83   %if (%1 < 0xa)
  84     debugShowCharacter BYTE ('0' + (%1))
  85   %else
  86     debugShowCharacter BYTE ('a' + ((%1) - 0xa))
  87   %endif
  88 %endmacro
  89
  90 %macro  debugNewline 0
  91     debugShowCharacter `\r`
  92     debugShowCharacter `\n`
  93 %endmacro
  94
  95 %macro  debugShowPostCode 1
  96     debugShowHexDigit (((%1) >> 4) & 0xf)
  97     debugShowHexDigit ((%1) & 0xf)
  98     debugNewline
  99 %endmacro
 100
 101 BITS    16
 102
 103 %macro  debugInitialize 0
 104   jmp  real16InitDebug
 105 real16InitDebugReturn:
 106 %endmacro
 107
 108 real16InitDebug:
 109     ;
 110     ; Set communications format
 111     ;
 112     outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)
 113
 114     ;
 115     ; Configure baud rate
 116     ;
 117     outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)
 118     outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)
 119
 120     ;
 121     ; Switch back to bank 0
 122     ;
 123     outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR
 124
 125     jmp     real16InitDebugReturn
 126