1951eb294c6c35eb71eca56f2aaab72fbdae8f54
[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec
1 ## @file UefiCpuPkg.dec
2 # This Package provides UEFI compatible CPU modules and libraries.
3 #
4 # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
5 #
6 # SPDX-License-Identifier: BSD-2-Clause-Patent
7 #
8 ##
9
10 [Defines]
11 DEC_SPECIFICATION = 0x00010005
12 PACKAGE_NAME = UefiCpuPkg
13 PACKAGE_UNI_FILE = UefiCpuPkg.uni
14 PACKAGE_GUID = 2171df9b-0d39-45aa-ac37-2de190010d23
15 PACKAGE_VERSION = 0.90
16
17 [Includes]
18 Include
19
20 [LibraryClasses]
21 ## @libraryclass Defines some routines that are generic for IA32 family CPU
22 ## to be UEFI specification compliant.
23 ##
24 UefiCpuLib|Include/Library/UefiCpuLib.h
25
26 ## @libraryclass Defines some routines that are used to register/manage/program
27 ## CPU features.
28 ##
29 RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
30
31 [LibraryClasses.IA32, LibraryClasses.X64]
32 ## @libraryclass Provides functions to manage MTRR settings on IA32 and X64 CPUs.
33 ##
34 MtrrLib|Include/Library/MtrrLib.h
35
36 ## @libraryclass Provides functions to manage the Local APIC on IA32 and X64 CPUs.
37 ##
38 LocalApicLib|Include/Library/LocalApicLib.h
39
40 ## @libraryclass Provides platform specific initialization functions in the SEC phase.
41 ##
42 PlatformSecLib|Include/Library/PlatformSecLib.h
43
44 ## @libraryclass Public include file for the SMM CPU Platform Hook Library.
45 ##
46 SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
47
48 ## @libraryclass Provides the CPU specific programming for PiSmmCpuDxeSmm module.
49 ##
50 SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
51
52 ## @libraryclass Provides functions to support MP services on CpuMpPei and CpuDxe module.
53 ##
54 MpInitLib|Include/Library/MpInitLib.h
55
56 ## @libraryclass Provides function to support VMGEXIT processing.
57 VmgExitLib|Include/Library/VmgExitLib.h
58
59 ## @libraryclass Provides function to get CPU cache information.
60 CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h
61
62 ## @libraryclass Provides function for loading microcode.
63 MicrocodeLib|Include/Library/MicrocodeLib.h
64
65 [Guids]
66 gUefiCpuPkgTokenSpaceGuid = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
67 gMsegSmramGuid = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
68
69 ## Include/Guid/CpuFeaturesSetDone.h
70 gEdkiiCpuFeaturesSetDoneGuid = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
71
72 ## Include/Guid/CpuFeaturesInitDone.h
73 gEdkiiCpuFeaturesInitDoneGuid = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
74
75 ## Include/Guid/MicrocodePatchHob.h
76 gEdkiiMicrocodePatchHobGuid = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
77
78 [Protocols]
79 ## Include/Protocol/SmmCpuService.h
80 gEfiSmmCpuServiceProtocolGuid = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
81 gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
82
83 ## Include/Protocol/SmMonitorInit.h
84 gEfiSmMonitorInitProtocolGuid = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
85
86 #
87 # [Error.gUefiCpuPkgTokenSpaceGuid]
88 # 0x80000001 | Invalid value provided.
89 #
90
91 [Ppis]
92 gEdkiiPeiMpServices2PpiGuid = { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
93
94 ## Include/Ppi/ShadowMicrocode.h
95 gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
96
97 ## Include/Ppi/RepublishSecPpi.h
98 gRepublishSecPpiPpiGuid = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
99
100 [PcdsFeatureFlag]
101 ## Indicates if SMM Profile will be enabled.
102 # If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
103 # In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
104 # In IA32 build, the page table memory is not marked as read-only when it is enabled.
105 # This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
106 # TRUE - SMM Profile will be enabled.<BR>
107 # FALSE - SMM Profile will be disabled.<BR>
108 # @Prompt Enable SMM Profile.
109 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
110
111 ## Indicates if the SMM profile log buffer is a ring buffer.
112 # If disabled, no additional log can be done when the buffer is full.<BR><BR>
113 # TRUE - the SMM profile log buffer is a ring buffer.<BR>
114 # FALSE - the SMM profile log buffer is a normal buffer.<BR>
115 # @Prompt The SMM profile log buffer is a ring buffer.
116 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
117
118 ## Indicates if SMM Startup AP in a blocking fashion.
119 # TRUE - SMM Startup AP in a blocking fashion.<BR>
120 # FALSE - SMM Startup AP in a non-blocking fashion.<BR>
121 # @Prompt SMM Startup AP in a blocking fashion.
122 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
123
124 ## Indicates if SMM Stack Guard will be enabled.
125 # If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
126 # TRUE - SMM Stack Guard will be enabled.<BR>
127 # FALSE - SMM Stack Guard will be disabled.<BR>
128 # @Prompt Enable SMM Stack Guard.
129 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
130
131 ## Indicates if BSP election in SMM will be enabled.
132 # If enabled, a BSP will be dynamically elected among all processors in each SMI.
133 # Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
134 # TRUE - BSP election in SMM will be enabled.<BR>
135 # FALSE - BSP election in SMM will be disabled.<BR>
136 # @Prompt Enable BSP election in SMM.
137 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
138
139 ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
140 # TRUE - SMM CPU hot-plug will be enabled.<BR>
141 # FALSE - SMM CPU hot-plug will be disabled.<BR>
142 # @Prompt SMM CPU hot-plug.
143 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
144
145 ## Indicates if SMM Debug will be enabled.
146 # If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
147 # TRUE - SMM Debug will be enabled.<BR>
148 # FALSE - SMM Debug will be disabled.<BR>
149 # @Prompt Enable SMM Debug.
150 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
151
152 ## Indicates if lock SMM Feature Control MSR.<BR><BR>
153 # TRUE - SMM Feature Control MSR will be locked.<BR>
154 # FALSE - SMM Feature Control MSR will not be locked.<BR>
155 # @Prompt Lock SMM Feature Control MSR.
156 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
157
158 [PcdsFixedAtBuild]
159 ## List of exception vectors which need switching stack.
160 # This PCD will only take into effect if PcdCpuStackGuard is enabled.
161 # By default exception #DD(8), #PF(14) are supported.
162 # @Prompt Specify exception vectors which need switching stack.
163 gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
164
165 ## Size of good stack for an exception.
166 # This PCD will only take into effect if PcdCpuStackGuard is enabled.
167 # @Prompt Specify size of good stack of exception which need switching stack.
168 gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
169
170 ## Count of pre allocated SMM MP tokens per chunk.
171 # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
172 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
173
174 ## Area of memory where the SEV-ES work area block lives.
175 # @Prompt Configure the SEV-ES work area base
176 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005
177
178 ## Size of teh area of memory where the SEV-ES work area block lives.
179 # @Prompt Configure the SEV-ES work area base
180 gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
181
182 [PcdsFixedAtBuild, PcdsPatchableInModule]
183 ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
184 # @Prompt Configure base address of CPU Local APIC
185 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
186 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
187
188 ## Specifies delay value in microseconds after sending out an INIT IPI.
189 # @Prompt Configure delay value after send an INIT IPI
190 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
191
192 ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
193 ## aligns the address on a 4-KByte boundary.
194 # @Prompt Configure stack size for Application Processor (AP)
195 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
196
197 ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
198 # @Prompt Stack size in the temporary RAM.
199 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
200
201 ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
202 # @Prompt SMM profile data buffer size.
203 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
204
205 ## Specifies stack size in bytes for each processor in SMM.
206 # @Prompt Processor stack size in SMM.
207 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
208
209 ## Specifies shadow stack size in bytes for each processor in SMM.
210 # @Prompt Processor shadow stack size in SMM.
211 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
212
213 ## Indicates if SMM Code Access Check is enabled.
214 # If enabled, the SMM handler cannot execute the code outside SMM regions.
215 # This PCD is suggested to TRUE in production image.<BR><BR>
216 # TRUE - SMM Code Access Check will be enabled.<BR>
217 # FALSE - SMM Code Access Check will be disabled.<BR>
218 # @Prompt SMM Code Access Check.
219 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
220
221 ## Specifies the number of variable MTRRs reserved for OS use. The default number of
222 # MTRRs reserved for OS use is 2.
223 # @Prompt Number of reserved variable MTRRs.
224 gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
225
226 ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
227 # @Prompt STM exception stack size.
228 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
229
230 ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
231 # @Prompt MSEG size.
232 gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
233
234 ## Specifies the supported CPU features bit in array.
235 # @Prompt Supported CPU features.
236 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
237
238 ## Specifies if CPU features will be initialized after SMM relocation.
239 # @Prompt If CPU features will be initialized after SMM relocation.
240 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
241
242 ## Specifies if CPU features will be initialized during S3 resume.
243 # @Prompt If CPU features will be initialized during S3 resume.
244 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
245
246 ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
247 # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
248 # Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
249 # 6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
250 # Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
251 # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
252 gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
253
254 ## Specifies the periodic interval value in microseconds for the status check
255 # of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
256 # mode in DXE phase.
257 # @Prompt Periodic interval value in microseconds for AP status check in DXE.
258 gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
259
260 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
261 ## Specifies max supported number of Logical Processors.
262 # @Prompt Configure max supported number of Logical Processors
263 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
264 ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
265 # @Prompt Timeout for the BSP to detect all APs for the first time.
266 gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
267 ## Specifies the number of Logical Processors that are available in the
268 # preboot environment after platform reset, including BSP and APs. Possible
269 # values:<BR><BR>
270 # zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
271 # PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
272 # detection by the BSP.<BR>
273 # nonzero - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
274 # AP detection finishes only when the detected CPU count
275 # (BSP plus APs) reaches the value of
276 # PcdCpuBootLogicalProcessorNumber, regardless of how long
277 # that takes.<BR>
278 # @Prompt Number of Logical Processors available after platform reset.
279 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
280 ## Specifies the base address of the first microcode Patch in the microcode Region.
281 # @Prompt Microcode Region base address.
282 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
283 ## Specifies the size of the microcode Region.
284 # @Prompt Microcode Region size.
285 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
286 ## Specifies the AP wait loop state during POST phase.
287 # The value is defined as below.<BR><BR>
288 # 1: Place AP in the Hlt-Loop state.<BR>
289 # 2: Place AP in the Mwait-Loop state.<BR>
290 # 3: Place AP in the Run-Loop state.<BR>
291 # @Prompt The AP wait loop state.
292 # @ValidRange 0x80000001 | 1 - 3
293 gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
294 ## Specifies the AP target C-state for Mwait during POST phase.
295 # The default value 0 means C1 state.
296 # The value is defined as below.<BR><BR>
297 # @Prompt The specified AP target C-state for Mwait.
298 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
299
300 ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
301 # @Prompt AP synchronization timeout value in SMM.
302 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
303
304 ## Indicates the CPU synchronization method used when processing an SMI.
305 # 0x00 - Traditional CPU synchronization method.<BR>
306 # 0x01 - Relaxed CPU synchronization method.<BR>
307 # @Prompt SMM CPU Synchronization Method.
308 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
309
310 ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
311 # @Prompt The encoded values for target duty cycle modulation.
312 # @ValidRange 0x80000001 | 0 - 15
313 gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
314
315 ## Indicates if the current boot is a power-on reset.<BR><BR>
316 # TRUE - Current boot is a power-on reset.<BR>
317 # FALSE - Current boot is not a power-on reset.<BR>
318 # @Prompt Current boot is a power-on reset.
319 gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
320
321 [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
322 ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
323 # MMIO access is always allowed regardless of the value of this PCD.
324 # Loose of such restriction is only required by RAS components in X64 platforms.
325 # The PCD value is considered as constantly TRUE in IA32 platforms.
326 # When the PCD value is TRUE, page table is initialized to cover all memory spaces
327 # and the memory occupied by page table is protected by page table itself as read-only.
328 # In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
329 # In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
330 # (PcdHeapGuardPropertyMask in MdeModulePkg).
331 # In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
332 # or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
333 # TRUE - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
334 # FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
335 # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
336 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
337
338 [PcdsDynamic, PcdsDynamicEx]
339 ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
340 # @Prompt The pointer to a CPU S3 data buffer.
341 # @ValidList 0x80000001 | 0
342 gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
343
344 ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
345 # @Prompt The pointer to CPU Hot Plug Data.
346 # @ValidList 0x80000001 | 0
347 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
348
349 ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
350 # @Prompt Processor feature capabilities.
351 # @ValidList 0x80000001 | 0
352 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
353
354 ## As input, specifies user's desired settings for enabling/disabling processor features.
355 ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
356 # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
357 # @ValidList 0x80000001 | 0
358 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
359
360 ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
361 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
362 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
363 # Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
364 # 0x0 - 4K.<BR>
365 # 0x1 - 8K.<BR>
366 # 0x2 - 16K.<BR>
367 # 0x3 - 32K.<BR>
368 # 0x4 - 64K.<BR>
369 # 0x5 - 128K.<BR>
370 # 0x6 - 256K.<BR>
371 # 0x7 - 512K.<BR>
372 # 0x8 - 1M.<BR>
373 # 0x9 - 2M.<BR>
374 # 0xA - 4M.<BR>
375 # 0xB - 8M.<BR>
376 # 0xC - 16M.<BR>
377 # 0xD - 32M.<BR>
378 # 0xE - 64M.<BR>
379 # 0xF - 128M.<BR>
380 # @Prompt The memory size used for processor trace if processor trace is enabled.
381 # @ValidRange 0x80000001 | 0 - 0xF
382 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
383
384 ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
385 # Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
386 # This PCD is ignored if CPU processor trace is disabled.<BR><BR>
387 # Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
388 # 0 - Single Range output scheme.<BR>
389 # 1 - ToPA(Table of physical address) scheme.<BR>
390 # @Prompt The processor trace output scheme used when processor trace is enabled.
391 # @ValidRange 0x80000001 | 0 - 1
392 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
393
394 ## This dynamic PCD indicates whether SEV-ES is enabled
395 # TRUE - SEV-ES is enabled
396 # FALSE - SEV-ES is not enabled
397 # @Prompt SEV-ES Status
398 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016
399
400 ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
401 # features VMGEXIT defined in the version 2 of GHCB spec.
402 # @Prompt GHCB Hypervisor Features
403 gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018
404
405 [UserExtensions.TianoCore."ExtraFiles"]
406 UefiCpuPkgExtra.uni