UefiCpuPkg/UefiCpuPkg.dec

   1 ## @file  UefiCpuPkg.dec
   2 # This Package provides UEFI compatible CPU modules and libraries.
   3 #
   4 # Copyright (c) 2007 - 2023, Intel Corporation. All rights reserved.<BR>
   5 #
   6 # SPDX-License-Identifier: BSD-2-Clause-Patent
   7 #
   8 ##
   9
  10 [Defines]
  11   DEC_SPECIFICATION              = 0x00010005
  12   PACKAGE_NAME                   = UefiCpuPkg
  13   PACKAGE_UNI_FILE               = UefiCpuPkg.uni
  14   PACKAGE_GUID                   = 2171df9b-0d39-45aa-ac37-2de190010d23
  15   PACKAGE_VERSION                = 0.90
  16
  17 [Includes]
  18   Include
  19
  20 [LibraryClasses]
  21   ##  @libraryclass  Defines some routines that are generic for IA32 family CPU
  22   ##                 to be UEFI specification compliant.
  23   ##
  24   UefiCpuLib|Include/Library/UefiCpuLib.h
  25
  26   ##  @libraryclass  Defines some routines that are used to register/manage/program
  27   ##                 CPU features.
  28   ##
  29   RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h
  30
  31 [LibraryClasses.IA32, LibraryClasses.X64]
  32   ##  @libraryclass  Provides functions to manage MTRR settings on IA32 and X64 CPUs.
  33   ##
  34   MtrrLib|Include/Library/MtrrLib.h
  35
  36   ##  @libraryclass  Provides functions to manage the Local APIC on IA32 and X64 CPUs.
  37   ##
  38   LocalApicLib|Include/Library/LocalApicLib.h
  39
  40   ##  @libraryclass  Provides platform specific initialization functions in the SEC phase.
  41   ##
  42   PlatformSecLib|Include/Library/PlatformSecLib.h
  43
  44   ##  @libraryclass  Public include file for the SMM CPU Platform Hook Library.
  45   ##
  46   SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h
  47
  48   ##  @libraryclass  Provides the CPU specific programming for PiSmmCpuDxeSmm module.
  49   ##
  50   SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h
  51
  52   ##  @libraryclass  Provides functions to support MP services on CpuMpPei and CpuDxe module.
  53   ##
  54   MpInitLib|Include/Library/MpInitLib.h
  55
  56   ##  @libraryclass  Provides function to support CcExit processing.
  57   CcExitLib|Include/Library/CcExitLib.h
  58
  59   ##  @libraryclass  Provides function to get CPU cache information.
  60   CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h
  61
  62   ##  @libraryclass  Provides function for loading microcode.
  63   MicrocodeLib|Include/Library/MicrocodeLib.h
  64
  65   ##  @libraryclass  Provides function for manipulating x86 paging structures.
  66   CpuPageTableLib|Include/Library/CpuPageTableLib.h
  67
  68 [Guids]
  69   gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}
  70   gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}
  71
  72   ## Include/Guid/CpuFeaturesSetDone.h
  73   gEdkiiCpuFeaturesSetDoneGuid   = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}
  74
  75   ## Include/Guid/CpuFeaturesInitDone.h
  76   gEdkiiCpuFeaturesInitDoneGuid  = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}
  77
  78   ## Include/Guid/MicrocodePatchHob.h
  79   gEdkiiMicrocodePatchHobGuid    = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}
  80
  81   ## Include/Guid/SmmBaseHob.h
  82   gSmmBaseHobGuid      = { 0xc2217ba7, 0x03bb, 0x4f63, {0xa6, 0x47, 0x7c, 0x25, 0xc5, 0xfc, 0x9d, 0x73 }}
  83
  84 [Protocols]
  85   ## Include/Protocol/SmmCpuService.h
  86   gEfiSmmCpuServiceProtocolGuid   = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}
  87   gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}
  88
  89   ## Include/Protocol/SmMonitorInit.h
  90   gEfiSmMonitorInitProtocolGuid  = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}
  91
  92 [Protocols.RISCV64]
  93   #
  94   # Protocols defined for RISC-V systems
  95   #
  96   ## Include/Protocol/RiscVBootProtocol.h
  97   gRiscVEfiBootProtocolGuid  = { 0xccd15fec, 0x6f73, 0x4eec, { 0x83, 0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }}
  98
  99 #
 100 # [Error.gUefiCpuPkgTokenSpaceGuid]
 101 #   0x80000001 | Invalid value provided.
 102 #
 103
 104 [Ppis]
 105   gEdkiiPeiMpServices2PpiGuid =    { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}
 106
 107   ## Include/Ppi/ShadowMicrocode.h
 108   gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}
 109
 110   ## Include/Ppi/RepublishSecPpi.h
 111   gRepublishSecPpiPpiGuid   = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}
 112
 113 [PcdsFeatureFlag]
 114   ## Indicates if SMM Profile will be enabled.
 115   #  If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
 116   #  In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.
 117   #  In IA32 build, the page table memory is not marked as read-only when it is enabled.
 118   #  This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
 119   #   TRUE  - SMM Profile will be enabled.<BR>
 120   #   FALSE - SMM Profile will be disabled.<BR>
 121   # @Prompt Enable SMM Profile.
 122   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
 123
 124   ## Indicates if the SMM profile log buffer is a ring buffer.
 125   #  If disabled, no additional log can be done when the buffer is full.<BR><BR>
 126   #   TRUE  - the SMM profile log buffer is a ring buffer.<BR>
 127   #   FALSE - the SMM profile log buffer is a normal buffer.<BR>
 128   # @Prompt The SMM profile log buffer is a ring buffer.
 129   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
 130
 131   ## Indicates if SMM Startup AP in a blocking fashion.
 132   #   TRUE  - SMM Startup AP in a blocking fashion.<BR>
 133   #   FALSE - SMM Startup AP in a non-blocking fashion.<BR>
 134   # @Prompt SMM Startup AP in a blocking fashion.
 135   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
 136
 137   ## Indicates if SMM Stack Guard will be enabled.
 138   #  If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>
 139   #   TRUE  - SMM Stack Guard will be enabled.<BR>
 140   #   FALSE - SMM Stack Guard will be disabled.<BR>
 141   # @Prompt Enable SMM Stack Guard.
 142   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C
 143
 144   ## Indicates if BSP election in SMM will be enabled.
 145   #  If enabled, a BSP will be dynamically elected among all processors in each SMI.
 146   #  Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
 147   #   TRUE  - BSP election in SMM will be enabled.<BR>
 148   #   FALSE - BSP election in SMM will be disabled.<BR>
 149   # @Prompt Enable BSP election in SMM.
 150   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
 151
 152   ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
 153   #   TRUE  - SMM CPU hot-plug will be enabled.<BR>
 154   #   FALSE - SMM CPU hot-plug will be disabled.<BR>
 155   # @Prompt SMM CPU hot-plug.
 156   gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
 157
 158   ## Indicates if SMM Debug will be enabled.
 159   #  If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
 160   #   TRUE  - SMM Debug will be enabled.<BR>
 161   #   FALSE - SMM Debug will be disabled.<BR>
 162   # @Prompt Enable SMM Debug.
 163   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
 164
 165   ## Indicates if lock SMM Feature Control MSR.<BR><BR>
 166   #   TRUE  - SMM Feature Control MSR will be locked.<BR>
 167   #   FALSE - SMM Feature Control MSR will not be locked.<BR>
 168   # @Prompt Lock SMM Feature Control MSR.
 169   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
 170
 171   ## Indicates if SMRR will be enabled.<BR><BR>
 172   #   TRUE  - SMRR will be enabled.<BR>
 173   #   FALSE - SMRR will not be enabled.<BR>
 174   # @Prompt Enable SMRR.
 175   gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable|TRUE|BOOLEAN|0x3213210D
 176
 177   ## Indicates if SmmFeatureControl will be enabled.<BR><BR>
 178   #   TRUE  - SmmFeatureControl will be enabled.<BR>
 179   #   FALSE - SmmFeatureControl will not be enabled.<BR>
 180   # @Prompt Support SmmFeatureControl.
 181   gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable|TRUE|BOOLEAN|0x32132110
 182
 183 [PcdsFixedAtBuild]
 184   ## List of exception vectors which need switching stack.
 185   #  This PCD will only take into effect if PcdCpuStackGuard is enabled.
 186   #  By default exception #DD(8), #PF(14) are supported.
 187   # @Prompt Specify exception vectors which need switching stack.
 188   gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000
 189
 190   ## Size of good stack for an exception.
 191   #  This PCD will only take into effect if PcdCpuStackGuard is enabled.
 192   # @Prompt Specify size of good stack of exception which need switching stack.
 193   gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001
 194
 195   ## Count of pre allocated SMM MP tokens per chunk.
 196   # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.
 197   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002
 198
 199   ## Area of memory where the SEV-ES work area block lives.
 200   # @Prompt Configure the SEV-ES work area base
 201   gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005
 202
 203   ## Size of teh area of memory where the SEV-ES work area block lives.
 204   # @Prompt Configure the SEV-ES work area base
 205   gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006
 206
 207 [PcdsFixedAtBuild, PcdsPatchableInModule]
 208   ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
 209   # @Prompt Configure base address of CPU Local APIC
 210   # @Expression  0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
 211   gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
 212
 213   ## Specifies delay value in microseconds after sending out an INIT IPI.
 214   # @Prompt Configure delay value after send an INIT IPI
 215   gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
 216
 217   ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
 218   ## aligns the address on a 4-KByte boundary.
 219   # @Prompt Configure stack size for Application Processor (AP)
 220   gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003
 221
 222   ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.
 223   # @Prompt Stack size in the temporary RAM.
 224   gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
 225
 226   ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
 227   # @Prompt SMM profile data buffer size.
 228   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
 229
 230   ## Specifies stack size in bytes for each processor in SMM.
 231   # @Prompt Processor stack size in SMM.
 232   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
 233
 234   ## Specifies shadow stack size in bytes for each processor in SMM.
 235   # @Prompt Processor shadow stack size in SMM.
 236   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E
 237
 238   ## Indicates if SMM Code Access Check is enabled.
 239   #  If enabled, the SMM handler cannot execute the code outside SMM regions.
 240   #  This PCD is suggested to TRUE in production image.<BR><BR>
 241   #   TRUE  - SMM Code Access Check will be enabled.<BR>
 242   #   FALSE - SMM Code Access Check will be disabled.<BR>
 243   # @Prompt SMM Code Access Check.
 244   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
 245
 246   ## Specifies the number of variable MTRRs reserved for OS use. The default number of
 247   #  MTRRs reserved for OS use is 2.
 248   # @Prompt Number of reserved variable MTRRs.
 249   gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015
 250
 251   ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.
 252   # @Prompt STM exception stack size.
 253   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111
 254
 255   ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.
 256   # @Prompt MSEG size.
 257   gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112
 258
 259   ## Specifies the supported CPU features bit in array.
 260   # @Prompt Supported CPU features.
 261   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016
 262
 263   ## Specifies if CPU features will be initialized after SMM relocation.
 264   # @Prompt If CPU features will be initialized after SMM relocation.
 265   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C
 266
 267   ## Specifies if CPU features will be initialized during S3 resume.
 268   # @Prompt If CPU features will be initialized during S3 resume.
 269   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D
 270
 271   ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.
 272   # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.
 273   #   Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)
 274   #   6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)
 275   #   Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)
 276   # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX
 277   gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113
 278
 279   ## Specifies the periodic interval value in microseconds for the status check
 280   #  of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking
 281   #  mode in DXE phase.
 282   # @Prompt Periodic interval value in microseconds for AP status check in DXE.
 283   gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E
 284
 285 [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
 286   ## Specifies max supported number of Logical Processors.
 287   # @Prompt Configure max supported number of Logical Processors
 288   gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
 289   ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
 290   # @Prompt Timeout for the BSP to detect all APs for the first time.
 291   gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004
 292   ## Specifies the number of Logical Processors that are available in the
 293   #  preboot environment after platform reset, including BSP and APs. Possible
 294   #  values:<BR><BR>
 295   #  zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and
 296   #                   PcdCpuApInitTimeOutInMicroSeconds limits the initial AP
 297   #                   detection by the BSP.<BR>
 298   #  nonzero        - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial
 299   #                   AP detection finishes only when the detected CPU count
 300   #                   (BSP plus APs) reaches the value of
 301   #                   PcdCpuBootLogicalProcessorNumber, regardless of how long
 302   #                   that takes.<BR>
 303   # @Prompt Number of Logical Processors available after platform reset.
 304   gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008
 305   ## Specifies the base address of the first microcode Patch in the microcode Region.
 306   # @Prompt Microcode Region base address.
 307   gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005
 308   ## Specifies the size of the microcode Region.
 309   # @Prompt Microcode Region size.
 310   gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
 311   ## Specifies the AP wait loop state during POST phase.
 312   #  The value is defined as below.<BR><BR>
 313   #  1: Place AP in the Hlt-Loop state.<BR>
 314   #  2: Place AP in the Mwait-Loop state.<BR>
 315   #  3: Place AP in the Run-Loop state.<BR>
 316   # @Prompt The AP wait loop state.
 317   # @ValidRange  0x80000001 | 1 - 3
 318   gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006
 319   ## Specifies the AP target C-state for Mwait during POST phase.
 320   #  The default value 0 means C1 state.
 321   #  The value is defined as below.<BR><BR>
 322   # @Prompt The specified AP target C-state for Mwait.
 323   gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007
 324
 325   ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
 326   # @Prompt AP synchronization timeout value in SMM.
 327   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
 328
 329   ## Indicates the CPU synchronization method used when processing an SMI.
 330   #   0x00  - Traditional CPU synchronization method.<BR>
 331   #   0x01  - Relaxed CPU synchronization method.<BR>
 332   # @Prompt SMM CPU Synchronization Method.
 333   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
 334
 335   ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.
 336   # @Prompt The encoded values for target duty cycle modulation.
 337   # @ValidRange  0x80000001 | 0 - 15
 338   gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A
 339
 340   ## Indicates if the current boot is a power-on reset.<BR><BR>
 341   #   TRUE  - Current boot is a power-on reset.<BR>
 342   #   FALSE - Current boot is not a power-on reset.<BR>
 343   # @Prompt Current boot is a power-on reset.
 344   gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B
 345
 346 [PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]
 347   ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
 348   #  MMIO access is always allowed regardless of the value of this PCD.
 349   #  Loose of such restriction is only required by RAS components in X64 platforms.
 350   #  The PCD value is considered as constantly TRUE in IA32 platforms.
 351   #  When the PCD value is TRUE, page table is initialized to cover all memory spaces
 352   #  and the memory occupied by page table is protected by page table itself as read-only.
 353   #  In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).
 354   #  In X64 build, it could not be enabled also at the same time with heap guard feature for SMM
 355   #  (PcdHeapGuardPropertyMask in MdeModulePkg).
 356   #  In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)
 357   #  or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.
 358   #   TRUE  - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>
 359   #   FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>
 360   # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
 361   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
 362
 363 [PcdsDynamic, PcdsDynamicEx]
 364   ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
 365   # @Prompt The pointer to a CPU S3 data buffer.
 366   # @ValidList   0x80000001 | 0
 367   gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
 368
 369   ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
 370   # @Prompt The pointer to CPU Hot Plug Data.
 371   # @ValidList   0x80000001 | 0
 372   gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
 373
 374   ## Indicates processor feature capabilities, each bit corresponding to a specific feature.
 375   # @Prompt Processor feature capabilities.
 376   # @ValidList   0x80000001 | 0
 377   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018
 378
 379   ## As input, specifies user's desired settings for enabling/disabling processor features.
 380   ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.
 381   # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.
 382   # @ValidList   0x80000001 | 0
 383   gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019
 384
 385   ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>
 386   #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
 387   #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>
 388   #  Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>
 389   #  0x0  -  4K.<BR>
 390   #  0x1  -  8K.<BR>
 391   #  0x2  -  16K.<BR>
 392   #  0x3  -  32K.<BR>
 393   #  0x4  -  64K.<BR>
 394   #  0x5  -  128K.<BR>
 395   #  0x6  -  256K.<BR>
 396   #  0x7  -  512K.<BR>
 397   #  0x8  -  1M.<BR>
 398   #  0x9  -  2M.<BR>
 399   #  0xA  -  4M.<BR>
 400   #  0xB  -  8M.<BR>
 401   #  0xC  -  16M.<BR>
 402   #  0xD  -  32M.<BR>
 403   #  0xE  -  64M.<BR>
 404   #  0xF  -  128M.<BR>
 405   # @Prompt The memory size used for processor trace if processor trace is enabled.
 406   # @ValidRange  0x80000001 | 0 - 0xF
 407   gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012
 408
 409   ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>
 410   #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>
 411   #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>
 412   #  Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>
 413   #  0 - Single Range output scheme.<BR>
 414   #  1 - ToPA(Table of physical address) scheme.<BR>
 415   # @Prompt The processor trace output scheme used when processor trace is enabled.
 416   # @ValidRange  0x80000001 | 0 - 1
 417   gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015
 418
 419   ## This dynamic PCD indicates whether SEV-ES is enabled
 420   #   TRUE  - SEV-ES is enabled
 421   #   FALSE - SEV-ES is not enabled
 422   # @Prompt SEV-ES Status
 423   gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016
 424
 425   ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR
 426   #  features VMGEXIT defined in the version 2 of GHCB spec.
 427   # @Prompt GHCB Hypervisor Features
 428   gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018
 429
 430 [UserExtensions.TianoCore."ExtraFiles"]
 431   UefiCpuPkgExtra.uni