Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PCI_DRC.ASL

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; This program and the accompanying materials are licensed and made available under
  11 ; the terms and conditions of the BSD License that accompanies this distribution.
  12 ; The full text of the license may be found at
  13 ; http://opensource.org/licenses/bsd-license.php.
  14 ;
  15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17 ;
  18 ;*                                                                        *;
  19 ;*                                                                        *;
  20 ;**************************************************************************/
  21
  22
  23
  24 Scope (\_SB.PCI0)
  25 {
  26
  27   Device(PDRC)   // PCI Device Resource Consumption
  28   {
  29     Name(_HID,EISAID("PNP0C02"))
  30
  31     Name(_UID,1)
  32
  33     Name(BUF0,ResourceTemplate()
  34     {
  35       //
  36       // PCI Express BAR _BAS and _LEN will be updated in _CRS below according to B0:D0:F0:Reg.60h
  37       // Forced hard code at the moment.
  38       //
  39       //Memory32Fixed(ReadWrite,0,0,PCIX)       // PCIEX BAR
  40       Memory32Fixed(ReadWrite,0x0E0000000,0x010000000,PCIX)
  41
  42       //
  43       // SPI BAR. Check if the hard code meets the real configuration.
  44       // If not, dynamically update it like the _CRS method below.
  45       //
  46       Memory32Fixed(ReadWrite,0x0FED01000,0x01000,SPIB) // SPI BAR
  47
  48       //
  49       // PMC BAR. Check if the hard code meets the real configuration.
  50       // If not, dynamically update it like the _CRS method below.
  51       //
  52       Memory32Fixed(ReadWrite,0x0FED03000,0x01000,PMCB) // PMC BAR
  53
  54       //
  55       // SMB BAR. Check if the hard code meets the real configuration.
  56       // If not, dynamically update it like the _CRS method below.
  57       //
  58       Memory32Fixed(ReadWrite,0x0FED04000,0x01000,SMBB) // SMB BAR
  59
  60       //
  61       // IO BAR. Check if the hard code meets the real configuration.
  62       // If not, dynamically update it like the _CRS method below.
  63       //
  64       Memory32Fixed(ReadWrite,0x0FED0C000,0x04000,IOBR) // IO BAR
  65
  66       //
  67       // ILB BAR. Check if the hard code meets the real configuration.
  68       // If not, dynamically update it like the _CRS method below.
  69       //
  70       Memory32Fixed(ReadWrite,0x0FED08000,0x01000,ILBB) // ILB BAR
  71
  72       //
  73       // RCRB BAR _BAS will be updated in _CRS below according to B0:D31:F0:Reg.F0h
  74       //
  75       Memory32Fixed(ReadWrite,0x0FED1C000,0x01000,RCRB) // RCRB BAR
  76
  77       //
  78       // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
  79       //
  80       Memory32Fixed (ReadOnly, 0x0FEE00000, 0x0100000, LIOH)
  81
  82       //
  83       // MPHY BAR. Check if the hard code meets the real configuration.
  84       // If not, dynamically update it like the _CRS method below.
  85       //
  86       Memory32Fixed(ReadWrite,0x0FEF00000,0x0100000,MPHB)       // MPHY BAR
  87     })
  88
  89     Method(_CRS,0,Serialized)
  90     {
  91
  92       Return(BUF0)
  93     }
  94
  95   }
  96 }