Vlv2DeviceRefCodePkg/AcpiTablesPCAT/Pch.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c) 2012  - 2016, Intel Corporation. All rights reserved    *;
   9 ;
  10 ; This program and the accompanying materials are licensed and made available under
  11 ; the terms and conditions of the BSD License that accompanies this distribution.
  12 ; The full text of the license may be found at
  13 ; http://opensource.org/licenses/bsd-license.php.
  14 ;
  15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17 ;
  18 ;*                                                                        *;
  19 ;*                                                                        *;
  20 ;**************************************************************************/
  21
  22
  23 Scope(\)
  24 {
  25   //
  26   // Define VLV ABASE I/O as an ACPI operating region. The base address
  27   // can be found in Device 31, Registers 40-43h.
  28   //
  29   OperationRegion(PMIO, SystemIo, \PMBS, 0x46)
  30   Field(PMIO, ByteAcc, NoLock, Preserve)
  31   {
  32     ,      8,
  33     PWBS,  1,       // Power Button Status
  34     Offset(0x20),
  35     ,      13,
  36     PMEB,  1,     // PME_B0_STS
  37     Offset(0x42),     // General Purpose Control
  38     ,      1,
  39     GPEC,  1
  40   }
  41   Field(PMIO, ByteAcc, NoLock, WriteAsZeros)
  42   {
  43     Offset(0x20),     // GPE0 Status
  44     ,      4,
  45     PSCI,  1,       // PUNIT SCI Status
  46     SCIS,  1        // GUNIT SCI Status
  47   }
  48
  49
  50
  51   //
  52   // Define a Memory Region that will allow access to the PMC
  53   // Register Block.  Note that in the Intel Reference Solution, the PMC
  54   // will get fixed up dynamically during POST.
  55   //
  56   OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
  57   Field(PMCR,DWordAcc,Lock,Preserve)
  58   {
  59     Offset(0x00),   //  Function Disable Register
  60     L10D,  1,         //  (0) LPIO1 DMA Disable
  61     L11D,  1,         //  (1) LPIO1 PWM #1 Disable
  62     L12D,  1,         //  (2) LPIO1 PWM #2 Disable
  63     L13D,  1,         //  (3) LPIO1 HS-UART #1 Disable
  64     L14D,  1,         //  (4) LPIO1 HS-UART #2 Disable
  65     L15D,  1,         //  (5) LPIO1 SPI Disable
  66     ,          2,     //  (6:7) Reserved
  67     SD1D,  1,         //  (8) SCC SDIO #1 Disable
  68     SD2D,  1,         //  (9) SCC SDIO #2 Disable
  69     SD3D,  1,         //  (10) SCC SDIO #3 Disable
  70     HSID,  1,         //  (11)
  71     HDAD,  1,         //  (12) Azalia Disable
  72     LPED,  1,         //  (13) LPE Disable
  73     OTGD,  1,         //  (14) USB OTG Disable
  74     ,          1,     //  (15) USH Disable
  75     ,          1,     //  (16)
  76     ,          1,     //  (17)
  77     ,          1,     //  (18) USB Disable
  78     ,          1,     //  (19) SEC Disable
  79     RP1D,  1,         //  (20) Root Port 0 Disable
  80     RP2D,  1,         //  (21) Root Port 1 Disable
  81     RP3D,  1,         //  (22) Root Port 2 Disable
  82     RP4D,  1,         //  (23) Root Port 3 Disable
  83     L20D,  1,         //  (24) LPIO2 DMA Disable
  84     L21D,  1,         //  (25) LPIO2 I2C #1 Disable
  85     L22D,  1,         //  (26) LPIO2 I2C #2 Disable
  86     L23D,  1,         //  (27) LPIO2 I2C #3 Disable
  87     L24D,  1,         //  (28) LPIO2 I2C #4 Disable
  88     L25D,  1,         //  (29) LPIO2 I2C #5 Disable
  89     L26D,  1,         //  (30) LPIO2 I2C #6 Disable
  90     L27D,  1          //  (31) LPIO2 I2C #7 Disable
  91   }
  92
  93
  94   OperationRegion(CLKC, SystemMemory, \PCLK, 0x18)// PMC CLK CTL Registers
  95   Field(CLKC,DWordAcc,Lock,Preserve)
  96   {
  97     Offset(0x00),   //  PLT_CLK_CTL_0
  98     CKC0, 2,
  99     CKF0, 1,
 100     ,     29,
 101     Offset(0x04),   //  PLT_CLK_CTL_1
 102     CKC1, 2,
 103     CKF1, 1,
 104     ,     29,
 105     Offset(0x08),   //  PLT_CLK_CTL_2
 106     CKC2,  2,
 107     CKF2, 1,
 108     ,     29,
 109     Offset(0x0C),   //  PLT_CLK_CTL_3
 110     CKC3,  2,
 111     CKF3, 1,
 112     ,     29,
 113     Offset(0x10),   //  PLT_CLK_CTL_4
 114     CKC4,  2,
 115     CKF4, 1,
 116     ,     29,
 117     Offset(0x14),   //  PLT_CLK_CTL_5
 118     CKC5,  2,
 119     CKF5, 1,
 120     ,     29,
 121   }
 122 } //end Scope(\)
 123
 124 scope (\_SB)
 125 {
 126   Device(LPEA)
 127   {
 128     Name (_ADR, 0)
 129     Name (_HID, "80860F28")
 130     Name (_CID, "80860F28")
 131     //Name (_CLS, Package (3) {0x04, 0x01, 0x00})
 132     Name (_DDN, "Intel(R) Low Power Audio Controller - 80860F28")
 133     Name (_SUB, "80867270")
 134     Name (_UID, 1)
 135     Name (_DEP, Package() {\_SB.I2C2.RTEK})
 136     Name(_PR0,Package() {PLPE})
 137
 138     Method (_STA, 0x0, NotSerialized)
 139     {
 140       If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 0)))
 141       {
 142         If(LEqual(LPAD, 1))
 143         {
 144           Return (0xF)
 145         }
 146       }
 147       Return (0x0)
 148     }
 149
 150     Method (_DIS, 0x0, NotSerialized)
 151     {
 152       //Add a dummy disable function
 153     }
 154
 155     Name (RBUF, ResourceTemplate ()
 156       {
 157         Memory32Fixed (ReadWrite, 0xFE400000, 0x00200000, BAR0)  // MMIO 1 - LPE MMIO
 158         Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
 159         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
 160         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
 161         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {25}
 162         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {26}
 163         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {27}
 164         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {28}
 165         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
 166         GpioInt(Edge, ActiveBoth, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO2") {28} //  Audio jack interrupt
 167       }
 168     )
 169
 170     Method (_CRS, 0x0, NotSerialized)
 171     {
 172       CreateDwordField(^RBUF, ^BAR0._BAS, B0BA)
 173       Store(LPE0, B0BA)
 174       CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
 175       Store(LPE1, B1BA)
 176       CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
 177       Store(LPE2, B2BA)
 178       Return (RBUF)
 179     }
 180
 181     OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
 182     Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
 183     {
 184       Offset (0x84),
 185       PSAT,   32
 186     }
 187
 188     PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
 189     {
 190       Method (_STA)
 191       {
 192         Return (1)      // Power Resource is always available.
 193       }
 194
 195       Method (_ON)
 196       {
 197         And(PSAT, 0xfffffffC, PSAT)
 198         OR(PSAT, 0X00000000, PSAT)
 199       }
 200
 201       Method (_OFF)
 202       {
 203         OR(PSAT, 0x00000003, PSAT)
 204         OR(PSAT, 0X00000000, PSAT)
 205       }
 206     } // End PLPE
 207   } // End "Low Power Engine Audio"
 208
 209   Device(LPA2)
 210   {
 211     Name (_ADR, 0)
 212     Name (_HID, "LPE0F28")  // _HID: Hardware ID
 213     Name (_CID, "LPE0F28")  // _CID: Compatible ID
 214     Name (_DDN, "Intel(R) SST Audio - LPE0F28")  // _DDN: DOS Device Name
 215     Name (_SUB, "80867270")
 216     Name (_UID, 1)
 217     Name (_DEP, Package() {\_SB.I2C2.RTEK})
 218     Name(_PR0,Package() {PLPE})
 219
 220     Method (_STA, 0x0, NotSerialized)
 221     {
 222       If (LAnd(LAnd(LEqual(LPEE, 2), LEqual(LPED, 0)), LEqual(OSEL, 1)))
 223       {
 224         If(LEqual(LPAD, 1))
 225         {
 226           Return (0xF)
 227         }
 228       }
 229       Return (0x0)
 230     }
 231
 232     Method (_DIS, 0x0, NotSerialized)
 233     {
 234       //Add a dummy disable function
 235     }
 236
 237     Name (RBUF, ResourceTemplate ()
 238       {
 239         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00100000, BAR2)  // LPE Memory Bar Allocate during post
 240         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00000100, SHIM)
 241         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, MBOX)
 242         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00014000, IRAM)
 243         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00028000, DRAM)
 244         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {29}
 245         Memory32Fixed (ReadWrite, 0xFE830000, 0x00001000, BAR1)  // MMIO 2 - Shadowed PCI Config Space
 246       }
 247     )
 248
 249     Method (_CRS, 0x0, NotSerialized)
 250     {
 251       CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
 252       Add(LPE0, 0x140000, SHBA)
 253       CreateDwordField(^RBUF, ^MBOX._BAS, MBBA)
 254       Add(LPE0, 0x144000, MBBA)
 255       CreateDwordField(^RBUF, ^IRAM._BAS, IRBA)
 256       Add(LPE0, 0xC0000, IRBA)
 257       CreateDwordField(^RBUF, ^DRAM._BAS, DRBA)
 258       Add(LPE0, 0x100000, DRBA)
 259       CreateDwordField(^RBUF, ^BAR1._BAS, B1BA)
 260       Store(LPE1, B1BA)
 261       CreateDwordField(^RBUF, ^BAR2._BAS, B2BA)
 262       Store(LPE2, B2BA)
 263       Return (RBUF)
 264     }
 265
 266     OperationRegion (KEYS, SystemMemory, LPE1, 0x100)
 267     Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
 268     {
 269       Offset (0x84),
 270       PSAT,   32
 271     }
 272
 273     PowerResource(PLPE, 0, 0)   // Power Resource for LPEA
 274     {
 275       Method (_STA)
 276       {
 277         Return (1)      // Power Resource is always available.
 278       }
 279
 280       Method (_ON)
 281       {
 282         And(PSAT, 0xfffffffC, PSAT)
 283         OR(PSAT, 0X00000000, PSAT)
 284       }
 285
 286       Method (_OFF)
 287       {
 288         OR(PSAT, 0x00000003, PSAT)
 289         OR(PSAT, 0X00000000, PSAT)
 290       }
 291     } // End PLPE
 292
 293     Device (ADMA)
 294     {
 295       Name (_ADR, Zero)  // _ADR: Address
 296       Name (_HID, "DMA0F28")  // _HID: Hardware ID
 297       Name (_CID, "DMA0F28")  // _CID: Compatible ID
 298       Name (_DDN, "Intel(R) Audio  DMA0 - DMA0F28")  // _DDN: DOS Device Name
 299       Name (_UID, One)  // _UID: Unique ID
 300       Name (RBUF, ResourceTemplate ()
 301       {
 302         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, DMA0)  // LPE BASE + LPE DMA0 offset
 303         Memory32Fixed (ReadWrite, 0x55AA55AA, 0x00001000, SHIM)  // LPE BASE + LPE SHIM offset
 304         Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {24}
 305       })
 306
 307       Method (_CRS, 0, NotSerialized)   // _CRS: Current Resource Settings
 308       {
 309         CreateDwordField(^RBUF, ^DMA0._BAS, D0BA)
 310         Add(LPE0, 0x98000, D0BA)
 311         CreateDwordField(^RBUF, ^SHIM._BAS, SHBA)
 312         Add(LPE0, 0x140000, SHBA)
 313         Return (RBUF)
 314       }
 315     }
 316   } // End "Low Power Engine Audio" for Android
 317 }
 318
 319 scope (\_SB.PCI0)
 320 {
 321
 322   //
 323   // Serial ATA Host Controller - Device 19, Function 0
 324   //
 325
 326   Device(SATA)
 327   {
 328     Name(_ADR,0x00130000)
 329     //
 330     // SATA Methods pulled in via SSDT.
 331     //
 332
 333     OperationRegion(SATR, PCI_Config, 0x74,0x4)
 334     Field(SATR,WordAcc,NoLock,Preserve)
 335     {
 336       Offset(0x00), // 0x74, PMCR
 337       ,   8,
 338       PMEE,   1,    //PME_EN
 339       ,   6,
 340       PMES,   1     //PME_STS
 341     }
 342
 343     Method (_STA, 0x0, NotSerialized)
 344     {
 345       Return(0xf)
 346     }
 347
 348     Method(_DSW, 3)
 349     {
 350     } // End _DSW
 351   }
 352
 353   //
 354   // For eMMC 4.41 PCI mode in order to present non-removable device under Windows environment
 355   //
 356   Device(EM41)
 357   {
 358     Name(_ADR,0x00100000)
 359     OperationRegion(SDIO, PCI_Config, 0x84,0x4)
 360     Field(SDIO,WordAcc,NoLock,Preserve)
 361     {
 362       Offset(0x00), // 0x84, PMCR
 363       ,   8,
 364       PMEE,   1,    //PME_EN
 365       ,   6,
 366       PMES,   1     //PME_STS
 367     }
 368
 369     Method (_STA, 0x0, NotSerialized)
 370     {
 371       If (LAnd(LEqual(PCIM, 1), LEqual(SD1D, 0)))
 372       {
 373         Return(0xF)
 374       }
 375       Else
 376       {
 377         Return(0x0)
 378       }
 379     }
 380
 381     Method(_DSW, 3)
 382     {
 383     } // End _DSW
 384
 385     Device (CARD)
 386     {
 387       Name (_ADR, 0x00000008)
 388       Method(_RMV, 0x0, NotSerialized)
 389       {
 390         Return (0)
 391       } // End _DSW
 392     }
 393   }
 394
 395   //
 396   // For eMMC 4.5 PCI mode in order to present non-removable device under Windows environment
 397   //
 398   Device(EM45)
 399   {
 400     Name(_ADR,0x00170000)
 401     OperationRegion(SDIO, PCI_Config, 0x84,0x4)
 402     Field(SDIO,WordAcc,NoLock,Preserve)
 403     {
 404       Offset(0x00), // 0x84, PMCR
 405       ,   8,
 406       PMEE,   1,    //PME_EN
 407       ,   6,
 408       PMES,   1     //PME_STS
 409     }
 410
 411     Method (_STA, 0x0, NotSerialized)
 412     {
 413       If (LAnd(LEqual(PCIM, 1), LEqual(HSID, 0)))
 414       {
 415         Return(0xF)
 416       }
 417       Else
 418       {
 419         Return(0x0)
 420       }
 421     }
 422
 423     Method(_DSW, 3)
 424     {
 425     } // End _DSW
 426
 427     Device (CARD)
 428     {
 429       Name (_ADR, 0x00000008)
 430       Method(_RMV, 0x0, NotSerialized)
 431       {
 432         Return (0)
 433       } // End _DSW
 434     }
 435   }
 436   //
 437   // For SD Host Controller (Bus 0x00 : Dev 0x12 : Func 0x00) PCI mode in order to present non-removable device under Windows environment
 438   //
 439   Device(SD12)
 440   {
 441     Name(_ADR,0x00120000)
 442
 443     Method (_STA, 0x0, NotSerialized)
 444     {
 445       //
 446       // PCIM>> 0:ACPI mode           1:PCI mode
 447       //
 448       If (LEqual(PCIM, 0)) {
 449         Return (0x0)
 450       }
 451
 452       //
 453       // If device is disabled.
 454       //
 455       If (LEqual(SD3D, 1))
 456       {
 457         Return (0x0)
 458       }
 459
 460       Return (0xF)
 461     }
 462
 463     Device (CARD)
 464     {
 465       Name (_ADR, 0x00000008)
 466       Method(_RMV, 0x0, NotSerialized)
 467       {
 468         // SDRM = 0 non-removable;
 469         If (LEqual(SDRM, 0))
 470         {
 471           Return (0)
 472         }
 473
 474         Return (1)
 475       }
 476     }
 477   }
 478
 479   // xHCI Controller - Device 20, Function 0
 480   include("PchXhci.asl")
 481
 482   //
 483   // High Definition Audio Controller - Device 27, Function 0
 484   //
 485   Device(HDEF)
 486   {
 487     Name(_ADR, 0x001B0000)
 488     include("PchAudio.asl")
 489
 490     Method (_STA, 0x0, NotSerialized)
 491     {
 492       If (LEqual(HDAD, 0))
 493       {
 494         Return(0xf)
 495       }
 496       Return(0x0)
 497     }
 498
 499     Method(_DSW, 3)
 500     {
 501     } // End _DSW
 502   } // end "High Definition Audio Controller"
 503
 504
 505
 506   //
 507   // PCIE Root Port #1
 508   //
 509   Device(RP01)
 510   {
 511     Name(_ADR, 0x001C0000)
 512     include("PchPcie.asl")
 513     Name(_PRW, Package() {9, 4})
 514
 515     Method(_PRT,0)
 516     {
 517       If(PICM) { Return(AR04) }// APIC mode
 518       Return (PR04) // PIC Mode
 519     } // end _PRT
 520   } // end "PCIE Root Port #1"
 521
 522   //
 523   // PCIE Root Port #2
 524   //
 525   Device(RP02)
 526   {
 527     Name(_ADR, 0x001C0001)
 528     include("PchPcie.asl")
 529     Name(_PRW, Package() {9, 4})
 530
 531     Method(_PRT,0)
 532     {
 533       If(PICM) { Return(AR05) }// APIC mode
 534       Return (PR05) // PIC Mode
 535     } // end _PRT
 536
 537   } // end "PCIE Root Port #2"
 538
 539   //
 540   // PCIE Root Port #3
 541   //
 542   Device(RP03)
 543   {
 544     Name(_ADR, 0x001C0002)
 545     include("PchPcie.asl")
 546     Name(_PRW, Package() {9, 4})
 547     Method(_PRT,0)
 548     {
 549       If(PICM) { Return(AR06) }// APIC mode
 550       Return (PR06) // PIC Mode
 551     } // end _PRT
 552
 553   } // end "PCIE Root Port #3"
 554
 555   //
 556   // PCIE Root Port #4
 557   //
 558   Device(RP04)
 559   {
 560     Name(_ADR, 0x001C0003)
 561     include("PchPcie.asl")
 562     Name(_PRW, Package() {9, 4})
 563     Method(_PRT,0)
 564     {
 565       If(PICM) { Return(AR07) }// APIC mode
 566       Return (PR07) // PIC Mode
 567     } // end _PRT
 568
 569   } // end "PCIE Root Port #4"
 570
 571
 572   Scope(\_SB)
 573   {
 574     //
 575     // Dummy power resource for USB D3 cold support
 576     //
 577     PowerResource(USBC, 0, 0)
 578     {
 579       Method(_STA) { Return (0xF) }
 580       Method(_ON) {}
 581       Method(_OFF) {}
 582     }
 583   }
 584   //
 585   // EHCI Controller - Device 29, Function 0
 586   //
 587   Device(EHC1)
 588   {
 589     Name(_ADR, 0x001D0000)
 590     Name(_DEP, Package(0x1)
 591     {
 592       PEPD
 593     })
 594     include("PchEhci.asl")
 595     Name(_PRW, Package() {0x0D, 4})
 596
 597     OperationRegion(USBR, PCI_Config, 0x54,0x4)
 598     Field(USBR,WordAcc,NoLock,Preserve)
 599     {
 600       Offset(0x00), // 0x54, PMCR
 601       ,   8,
 602       PMEE,   1,    //PME_EN
 603       ,   6,
 604       PMES,   1     //PME_STS
 605     }
 606
 607     Method (_STA, 0x0, NotSerialized)
 608     {
 609       If(LEqual(XHCI, 0))      //XHCI is not present. It means EHCI is there
 610       {
 611         Return (0xF)
 612       } Else
 613       {
 614         Return (0x0)
 615       }
 616     }
 617
 618     Method (_RMV, 0, NotSerialized)
 619     {
 620       Return (0x0)
 621     }
 622     //
 623     // Create a dummy PR3 method to indicate to the PCI driver
 624     // that the device is capable of D3 cold
 625     //
 626     Method(_PR3, 0x0, NotSerialized)
 627     {
 628       return (Package() {\_SB.USBC})
 629     }
 630
 631   } // end "EHCI Controller"
 632
 633   //
 634   // SMBus Controller - Device 31, Function 3
 635   //
 636   Device(SBUS)
 637   {
 638     Name(_ADR,0x001F0003)
 639     Include("PchSmb.asl")
 640   }
 641
 642   Device(SEC0)
 643   {
 644     Name (_ADR, 0x001a0000)                     // Device 0x1a, Function 0
 645     Name(_DEP, Package(0x1)
 646     {
 647       PEPD
 648     })
 649
 650
 651     OperationRegion (PMEB, PCI_Config, 0x84, 0x04)  //PMECTRLSTATUS
 652     Field (PMEB, WordAcc, NoLock, Preserve)
 653     {
 654       ,   8,
 655       PMEE,   1,    //bit8 PMEENABLE
 656       ,   6,
 657       PMES,   1     //bit15 PMESTATUS
 658     }
 659
 660     // Arg0 -- integer that contains the device wake capability control (0-disable 1- enable)
 661     // Arg1 -- integer that contains target system state (0-4)
 662     // Arg2 -- integer that contains the target device state
 663     Method (_DSW, 3, NotSerialized)   // _DSW: Device Sleep Wake
 664     {
 665     }
 666
 667     Method (_CRS, 0, NotSerialized)
 668     {
 669       Name (RBUF, ResourceTemplate ()
 670       {
 671         Memory32Fixed (ReadWrite, 0x1e000000, 0x2000000)
 672       })
 673
 674       If (LEqual(PAVP, 2))
 675       {
 676         Return (RBUF)
 677       }
 678       Return (ResourceTemplate() {})
 679     }
 680
 681     Method (_STA)
 682     {
 683       If (LNotEqual(PAVP, 0))
 684       {
 685         Return (0xF)
 686       }
 687       Return (0x0)
 688     }
 689   }   // Device(SEC0)
 690
 691 } // End scope (\_SB.PCI0)
 692