Vlv2DeviceRefCodePkg/AcpiTablesPCAT/PchSmb.asl

   1 /**************************************************************************;
   2 ;*                                                                        *;
   3 ;*                                                                        *;
   4 ;*    Intel Corporation - ACPI Reference Code for the Baytrail            *;
   5 ;*    Family of Customer Reference Boards.                                *;
   6 ;*                                                                        *;
   7 ;*                                                                        *;
   8 ;*    Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved   *;
   9 ;
  10 ; This program and the accompanying materials are licensed and made available under
  11 ; the terms and conditions of the BSD License that accompanies this distribution.
  12 ; The full text of the license may be found at
  13 ; http://opensource.org/licenses/bsd-license.php.
  14 ;
  15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17 ;
  18 ;*                                                                        *;
  19 ;*                                                                        *;
  20 ;**************************************************************************/
  21
  22
  23 // Define various SMBus PCI Configuration Space Registers.
  24
  25 OperationRegion(SMBP,PCI_Config,0x40,0xC0)
  26 Field(SMBP,DWordAcc,NoLock,Preserve)
  27 {
  28   ,     2,
  29   I2CE, 1
  30 }
  31
  32 // SMBus Send Byte - This function will write a single byte of
  33 // data to a specific Slave Device per SMBus Send Byte Protocol.
  34 //      Arg0 = Address
  35 //      Arg1 = Data
  36 //      Return: Success = 1
  37 //              Failure = 0
  38
  39       Method(SSXB,2,Serialized)
  40 {
  41   OperationRegion(SMPB,PCI_Config,0x20,4)
  42   Field(SMPB,DWordAcc,NoLock,Preserve)
  43   {
  44     ,     5,
  45     SBAR, 11
  46   }
  47
  48   // Define various SMBus IO Mapped Registers.
  49
  50   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
  51   Field(SMBI,ByteAcc,NoLock,Preserve)
  52   {
  53     HSTS, 8,        // 0 - Host Status Register
  54     Offset(0x02),
  55     HCON, 8,        // 2 - Host Control
  56     HCOM, 8,        // 3 - Host Command
  57     TXSA, 8,        // 4 - Transmit Slave Address
  58     DAT0, 8,        // 5 - Host Data 0
  59     DAT1, 8,        // 6 - Host Data 1
  60     HBDR, 8,        // 7 - Host Block Data
  61     PECR, 8,        // 8 - Packer Error Check
  62     RXSA, 8,        // 9 - Receive Slave Address
  63     SDAT, 16,       // A - Slave Data
  64   }
  65
  66   // Step 1:  Confirm the ICHx SMBus is ready to perform
  67   // communication.
  68
  69   If(STRT())
  70   {
  71     Return(0)
  72   }
  73
  74   // Step 2:  Initiate a Send Byte.
  75
  76   Store(0,I2CE)                           // Ensure SMbus Mode.
  77   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
  78   Store(Arg0,TXSA)                        // Write Address in TXSA.
  79   Store(Arg1,HCOM)                        // Data in HCOM.
  80
  81   // Set the SMBus Host control register to 0x48.
  82   //   Bit 7:    =  0  = reserved
  83   //   Bit 6:    =  1  = start
  84   //   Bit 5:    =  0  = disregard, I2C related bit
  85   //   Bits 4:2: = 001 = Byte Protocol
  86   //   Bit 1:    =  0  = Normal Function
  87   //   Bit 0:    =  0  = Disable interrupt generation
  88
  89   Store(0x48,HCON)
  90
  91   // Step 3:  Exit the Method correctly.
  92
  93   If(COMP)
  94   {
  95     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
  96     Return(1)                       // Return Success.
  97   }
  98
  99   Return(0)
 100 }
 101
 102 // SMBus Receive Byte - This function will write a single byte
 103 // of data to a specific Slave Device per SMBus Receive Byte
 104 // Protocol.
 105 //      Arg0 = Address
 106 //      Return: Success = Byte-Size Value
 107 //              Failure = Word-Size Value = FFFFh.
 108
 109 Method(SRXB,1,Serialized)
 110 {
 111   OperationRegion(SMPB,PCI_Config,0x20,4)
 112   Field(SMPB,DWordAcc,NoLock,Preserve)
 113   {
 114     ,     5,
 115     SBAR, 11
 116   }
 117
 118   // Define various SMBus IO Mapped Registers.
 119
 120   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 121   Field(SMBI,ByteAcc,NoLock,Preserve)
 122   {
 123     HSTS, 8,        // 0 - Host Status Register
 124     Offset(0x02),
 125     HCON, 8,        // 2 - Host Control
 126     HCOM, 8,        // 3 - Host Command
 127     TXSA, 8,        // 4 - Transmit Slave Address
 128     DAT0, 8,        // 5 - Host Data 0
 129     DAT1, 8,        // 6 - Host Data 1
 130     HBDR, 8,        // 7 - Host Block Data
 131     PECR, 8,        // 8 - Packer Error Check
 132     RXSA, 8,        // 9 - Receive Slave Address
 133     SDAT, 16,       // A - Slave Data
 134   }
 135   // Step 1:  Confirm the ICHx SMBus is ready to perform
 136   // communication.
 137
 138   If(STRT())
 139   {
 140     Return(0xFFFF)
 141   }
 142
 143   // Step 2:  Initiate a Receive Byte.
 144
 145   Store(0,I2CE)                           // Ensure SMbus Mode.
 146   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 147   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 148
 149   // Set the SMBus Host control register to 0x48.
 150   //   Bit 7:    =  0  = reserved
 151   //   Bit 6:    =  1  = start
 152   //   Bit 5:    =  0  = disregard, I2C related bit
 153   //   Bits 4:2: = 001 = Byte Protocol
 154   //   Bit 1:    =  0  = Normal Function
 155   //   Bit 0:    =  0  = Disable interrupt generation
 156
 157   Store(0x44,HCON)
 158
 159   // Step 3:  Exit the Method correctly.
 160
 161   If(COMP)
 162   {
 163     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 164     Return(DAT0)                    // Return Success.
 165   }
 166
 167   Return(0xFFFF)                          // Return Failure.
 168 }
 169
 170 // SMBus Write Byte - This function will write a single byte
 171 // of data to a specific Slave Device per SMBus Write Byte
 172 // Protocol.
 173 //      Arg0 = Address
 174 //      Arg1 = Command
 175 //      Arg2 = Data
 176 //      Return: Success = 1
 177 //              Failure = 0
 178
 179 Method(SWRB,3,Serialized)
 180 {
 181   OperationRegion(SMPB,PCI_Config,0x20,4)
 182   Field(SMPB,DWordAcc,NoLock,Preserve)
 183   {
 184     ,     5,
 185     SBAR, 11
 186   }
 187
 188   // Define various SMBus IO Mapped Registers.
 189
 190   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 191   Field(SMBI,ByteAcc,NoLock,Preserve)
 192   {
 193     HSTS, 8,        // 0 - Host Status Register
 194     Offset(0x02),
 195     HCON, 8,        // 2 - Host Control
 196     HCOM, 8,        // 3 - Host Command
 197     TXSA, 8,        // 4 - Transmit Slave Address
 198     DAT0, 8,        // 5 - Host Data 0
 199     DAT1, 8,        // 6 - Host Data 1
 200     HBDR, 8,        // 7 - Host Block Data
 201     PECR, 8,        // 8 - Packer Error Check
 202     RXSA, 8,        // 9 - Receive Slave Address
 203     SDAT, 16,       // A - Slave Data
 204   }
 205   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 206
 207   If(STRT())
 208   {
 209     Return(0)
 210   }
 211
 212   // Step 2:  Initiate a Write Byte.
 213
 214   Store(0,I2CE)                           // Ensure SMbus Mode.
 215   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 216   Store(Arg0,TXSA)                        // Write Address in TXSA.
 217   Store(Arg1,HCOM)                        // Command in HCOM.
 218   Store(Arg2,DAT0)                        // Data in DAT0.
 219
 220   // Set the SMBus Host control register to 0x48.
 221   //   Bit 7:    =  0  = reserved
 222   //   Bit 6:    =  1  = start
 223   //   Bit 5:    =  0  = disregard, I2C related bit
 224   //   Bits 4:2: = 010 = Byte Data Protocol
 225   //   Bit 1:    =  0  = Normal Function
 226   //   Bit 0:    =  0  = Disable interrupt generation
 227
 228   Store(0x48,HCON)
 229
 230   // Step 3:  Exit the Method correctly.
 231
 232   If(COMP)
 233   {
 234     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 235     Return(1)                       // Return Success.
 236   }
 237
 238   Return(0)                               // Return Failure.
 239 }
 240
 241 // SMBus Read Byte - This function will read a single byte of data
 242 // from a specific slave device per SMBus Read Byte Protocol.
 243 //      Arg0 = Address
 244 //      Arg1 = Command
 245 //      Return: Success = Byte-Size Value
 246 //              Failure = Word-Size Value
 247
 248 Method(SRDB,2,Serialized)
 249 {
 250   OperationRegion(SMPB,PCI_Config,0x20,4)
 251   Field(SMPB,DWordAcc,NoLock,Preserve)
 252   {
 253     ,     5,
 254     SBAR, 11
 255   }
 256
 257   // Define various SMBus IO Mapped Registers.
 258
 259   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 260   Field(SMBI,ByteAcc,NoLock,Preserve)
 261   {
 262     HSTS, 8,        // 0 - Host Status Register
 263     Offset(0x02),
 264     HCON, 8,        // 2 - Host Control
 265     HCOM, 8,        // 3 - Host Command
 266     TXSA, 8,        // 4 - Transmit Slave Address
 267     DAT0, 8,        // 5 - Host Data 0
 268     DAT1, 8,        // 6 - Host Data 1
 269     HBDR, 8,        // 7 - Host Block Data
 270     PECR, 8,        // 8 - Packer Error Check
 271     RXSA, 8,        // 9 - Receive Slave Address
 272     SDAT, 16,       // A - Slave Data
 273   }
 274   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 275
 276   If(STRT())
 277   {
 278     Return(0xFFFF)
 279   }
 280
 281   // Step 2:  Initiate a Read Byte.
 282
 283   Store(0,I2CE)                           // Ensure SMbus Mode.
 284   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 285   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 286   Store(Arg1,HCOM)                        // Command in HCOM.
 287
 288   // Set the SMBus Host control register to 0x48.
 289   //   Bit 7:    =  0  = reserved
 290   //   Bit 6:    =  1  = start
 291   //   Bit 5:    =  0  = disregard, I2C related bit
 292   //   Bits 4:2: = 010 = Byte Data Protocol
 293   //   Bit 1:    =  0  = Normal Function
 294   //   Bit 0:    =  0  = Disable interrupt generation
 295
 296   Store(0x48,HCON)
 297
 298   // Step 3:  Exit the Method correctly.
 299
 300   If(COMP)
 301   {
 302     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others..
 303     Return(DAT0)                    // Return Success.
 304   }
 305
 306   Return(0xFFFF)                          // Return Failure.
 307 }
 308
 309 // SMBus Write Word - This function will write a single word
 310 // of data to a specific Slave Device per SMBus Write Word
 311 // Protocol.
 312 //      Arg0 = Address
 313 //      Arg1 = Command
 314 //      Arg2 = Data (16 bits in size)
 315 //      Return: Success = 1
 316 //              Failure = 0
 317
 318 Method(SWRW,3,Serialized)
 319 {
 320   OperationRegion(SMPB,PCI_Config,0x20,4)
 321   Field(SMPB,DWordAcc,NoLock,Preserve)
 322   {
 323     ,     5,
 324     SBAR, 11
 325   }
 326
 327   // Define various SMBus IO Mapped Registers.
 328
 329   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 330   Field(SMBI,ByteAcc,NoLock,Preserve)
 331   {
 332     HSTS, 8,        // 0 - Host Status Register
 333     Offset(0x02),
 334         HCON, 8,        // 2 - Host Control
 335         HCOM, 8,        // 3 - Host Command
 336         TXSA, 8,        // 4 - Transmit Slave Address
 337         DAT0, 8,        // 5 - Host Data 0
 338         DAT1, 8,        // 6 - Host Data 1
 339         HBDR, 8,        // 7 - Host Block Data
 340         PECR, 8,        // 8 - Packer Error Check
 341         RXSA, 8,        // 9 - Receive Slave Address
 342         SDAT, 16,       // A - Slave Data
 343   }
 344   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 345
 346   If(STRT())
 347   {
 348     Return(0)
 349   }
 350
 351   // Step 2:  Initiate a Write Word.
 352
 353   Store(0,I2CE)                           // Ensure SMbus Mode.
 354   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 355   Store(Arg0,TXSA)                        // Write Address in TXSA.
 356   Store(Arg1,HCOM)                        // Command in HCOM.
 357   And(Arg2,0xFF,DAT1)                     // Low byte Data in DAT1.
 358   And(ShiftRight(Arg2,8),0xFF,DAT0)       // High byte Data in DAT0.
 359
 360   // Set the SMBus Host control register to 0x4C.
 361   //   Bit 7:    =  0  = reserved
 362   //   Bit 6:    =  1  = start
 363   //   Bit 5:    =  0  = disregard, I2C related bit
 364   //   Bits 4:2: = 011 = Word Data Protocol
 365   //   Bit 1:    =  0  = Normal Function
 366   //   Bit 0:    =  0  = Disable interrupt generation
 367
 368   Store(0x4C,HCON)
 369
 370   // Step 3:  Exit the Method correctly.
 371
 372   If(COMP())
 373   {
 374     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
 375     Return(1)                       // Return Success.
 376   }
 377
 378   Return(0)                               // Return Failure.
 379 }
 380
 381 // SMBus Read Word - This function will read a single byte of data
 382 // from a specific slave device per SMBus Read Word Protocol.
 383 //      Arg0 = Address
 384 //      Arg1 = Command
 385 //      Return: Success = Word-Size Value
 386 //              Failure = Dword-Size Value
 387
 388 Method(SRDW,2,Serialized)
 389 {
 390   OperationRegion(SMPB,PCI_Config,0x20,4)
 391   Field(SMPB,DWordAcc,NoLock,Preserve)
 392   {
 393     ,     5,
 394     SBAR, 11
 395   }
 396
 397   // Define various SMBus IO Mapped Registers.
 398
 399   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 400   Field(SMBI,ByteAcc,NoLock,Preserve)
 401   {
 402     HSTS, 8,        // 0 - Host Status Register
 403         Offset(0x02),
 404         HCON, 8,        // 2 - Host Control
 405         HCOM, 8,        // 3 - Host Command
 406         TXSA, 8,        // 4 - Transmit Slave Address
 407         DAT0, 8,        // 5 - Host Data 0
 408         DAT1, 8,        // 6 - Host Data 1
 409         HBDR, 8,        // 7 - Host Block Data
 410         PECR, 8,        // 8 - Packer Error Check
 411         RXSA, 8,        // 9 - Receive Slave Address
 412         SDAT, 16,       // A - Slave Data
 413   }
 414   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 415
 416   If(STRT())
 417   {
 418     Return(0xFFFF)
 419   }
 420
 421   // Step 2:  Initiate a Read Word.
 422
 423   Store(0,I2CE)                           // Ensure SMbus Mode.
 424   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 425   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 426   Store(Arg1,HCOM)                        // Command in HCOM.
 427
 428   // Set the SMBus Host control register to 0x4C.
 429   //   Bit 7:    =  0  = reserved
 430   //   Bit 6:    =  1  = start
 431   //   Bit 5:    =  0  = disregard, I2C related bit
 432   //   Bits 4:2: = 011 = Word Data Protocol
 433   //   Bit 1:    =  0  = Normal Function
 434   //   Bit 0:    =  0  = Disable interrupt generation
 435
 436   Store(0x4C,HCON)
 437
 438   // Step 3:  Exit the Method correctly.
 439
 440   If(COMP())
 441   {
 442     Or(HSTS,0xFF,HSTS)                      // Clear INUSE_STS and others.
 443     Return(Or(ShiftLeft(DAT0,8),DAT1))      // Return Success.
 444   }
 445
 446   Return(0xFFFFFFFF)                      // Return Failure.
 447 }
 448
 449 // SMBus Block Write - This function will write an entire block of data
 450 // to a specific slave device per SMBus Block Write Protocol.
 451 //      Arg0 = Address
 452 //      Arg1 = Command
 453 //      Arg2 = Buffer of Data to Write
 454 //      Arg3 = 1 = I2C Block Write, 0 = SMBus Block Write
 455 //      Return: Success = 1
 456 //              Failure = 0
 457
 458 Method(SBLW,4,Serialized)
 459 {
 460   OperationRegion(SMPB,PCI_Config,0x20,4)
 461   Field(SMPB,DWordAcc,NoLock,Preserve)
 462   {
 463     ,     5,
 464     SBAR, 11
 465   }
 466
 467   // Define various SMBus IO Mapped Registers.
 468
 469   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 470   Field(SMBI,ByteAcc,NoLock,Preserve)
 471   {
 472     HSTS, 8,        // 0 - Host Status Register
 473         Offset(0x02),
 474         HCON, 8,        // 2 - Host Control
 475         HCOM, 8,        // 3 - Host Command
 476         TXSA, 8,        // 4 - Transmit Slave Address
 477         DAT0, 8,        // 5 - Host Data 0
 478         DAT1, 8,        // 6 - Host Data 1
 479         HBDR, 8,        // 7 - Host Block Data
 480         PECR, 8,        // 8 - Packer Error Check
 481         RXSA, 8,        // 9 - Receive Slave Address
 482         SDAT, 16,       // A - Slave Data
 483   }
 484   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 485
 486   If(STRT())
 487   {
 488     Return(0)
 489   }
 490
 491   // Step 2:  Initiate a Block Write.
 492
 493   Store(Arg3,I2CE)                        // Select the proper protocol.
 494   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 495   Store(Arg0,TXSA)                        // Write Address in TXSA.
 496   Store(Arg1,HCOM)                        // Command in HCOM.
 497   Store(Sizeof(Arg2),DAT0)                // Count in DAT0.
 498   Store(0,Local1)                         // Init Pointer to Buffer.
 499   Store(DerefOf(Index(Arg2,0)),HBDR)      // First Byte in HBD Register.
 500
 501   // Set the SMBus Host control register to 0x48.
 502   //   Bit 7:    =  0  = reserved
 503   //   Bit 6:    =  1  = start
 504   //   Bit 5:    =  0  = disregard, I2C related bit
 505   //   Bits 4:2: = 101 = Block Protocol
 506   //   Bit 1:    =  0  = Normal Function
 507   //   Bit 0:    =  0  = Disable interrupt generation
 508
 509   Store(0x54,HCON)
 510
 511   // Step 3:  Send the entire Block of Data.
 512
 513   While(LGreater(Sizeof(Arg2),Local1))
 514   {
 515     // Wait up to 200ms for Host Status to get set.
 516
 517     Store(4000,Local0)              // 4000 * 50us = 200ms.
 518
 519     While(LAnd(LNot(And(HSTS,0x80)),Local0))
 520     {
 521       Decrement(Local0)       // Decrement Count.
 522       Stall(50)               // Delay = 50us.
 523     }
 524
 525     If(LNot(Local0))                // Timeout?
 526     {
 527       KILL()                  // Yes.  Kill Communication.
 528       Return(0)               // Return failure.
 529     }
 530
 531     Store(0x80,HSTS)                // Clear Host Status.
 532     Increment(Local1)               // Point to Next Byte.
 533
 534     // Place next byte in HBDR if last byte has not been sent.
 535
 536     If(LGreater(Sizeof(Arg2),Local1))
 537     {
 538       Store(DerefOf(Index(Arg2,Local1)),HBDR)
 539     }
 540   }
 541
 542   // Step 4:  Exit the Method correctly.
 543
 544   If(COMP())
 545   {
 546     Or(HSTS,0xFF,HSTS)              // Clear all status bits.
 547     Return(1)                       // Return Success.
 548   }
 549
 550   Return(0)                               // Return Failure.
 551 }
 552
 553 // SMBus Block Read - This function will read a block of data from
 554 // a specific slave device per SMBus Block Read Protocol.
 555 //      Arg0 = Address
 556 //      Arg1 = Command
 557 //      Arg2 = 1 = I2C Block Write, 0 = SMBus Block Write
 558 //      Return: Success = Data Buffer (First Byte = length)
 559 //              Failure = 0
 560
 561 Method(SBLR,3,Serialized)
 562 {
 563   OperationRegion(SMPB,PCI_Config,0x20,4)
 564   Field(SMPB,DWordAcc,NoLock,Preserve)
 565   {
 566     ,     5,
 567     SBAR, 11
 568   }
 569
 570   // Define various SMBus IO Mapped Registers.
 571
 572   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 573   Field(SMBI,ByteAcc,NoLock,Preserve)
 574   {
 575     HSTS, 8,        // 0 - Host Status Register
 576         Offset(0x02),
 577         HCON, 8,        // 2 - Host Control
 578         HCOM, 8,        // 3 - Host Command
 579         TXSA, 8,        // 4 - Transmit Slave Address
 580         DAT0, 8,        // 5 - Host Data 0
 581         DAT1, 8,        // 6 - Host Data 1
 582         HBDR, 8,        // 7 - Host Block Data
 583         PECR, 8,        // 8 - Packer Error Check
 584         RXSA, 8,        // 9 - Receive Slave Address
 585         SDAT, 16,       // A - Slave Data
 586   }
 587   Name(TBUF, Buffer(256) {})
 588
 589   // Step 1:  Confirm the ICHx SMBus is ready to perform communication.
 590
 591   If(STRT())
 592   {
 593     Return(0)
 594   }
 595
 596   // Step 2:  Initiate a Block Read.
 597
 598   Store(Arg2,I2CE)                        // Select the proper protocol.
 599   Store(0xBF,HSTS)                        // Clear all but INUSE_STS.
 600   Store(Or(Arg0,1),TXSA)                  // Read Address in TXSA.
 601   Store(Arg1,HCOM)                        // Command in HCOM.
 602
 603   // Set the SMBus Host control register to 0x48.
 604   //   Bit 7:    =  0  = reserved
 605   //   Bit 6:    =  1  = start
 606   //   Bit 5:    =  0  = disregard, I2C related bit
 607   //   Bits 4:2: = 101 = Block Protocol
 608   //   Bit 1:    =  0  = Normal Function
 609   //   Bit 0:    =  0  = Disable interrupt generation
 610
 611   Store(0x54,HCON)
 612
 613   // Step 3:  Wait up to 200ms to get the Data Count.
 614
 615   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 616
 617   While(LAnd(LNot(And(HSTS,0x80)),Local0))
 618   {
 619     Decrement(Local0)               // Decrement Count.
 620     Stall(50)                       // Delay = 50us.
 621   }
 622
 623   If(LNot(Local0))                        // Timeout?
 624   {
 625     KILL()                          // Yes.  Kill Communication.
 626     Return(0)                       // Return failure.
 627   }
 628
 629   Store(DAT0,Index(TBUF,0))               // Get the Data Count.
 630   Store(0x80,HSTS)                        // Clear Host Status.
 631   Store(1,Local1)                         // Local1 = Buffer Pointer.
 632
 633   // Step 4:  Get the Block Data and store it.
 634
 635   While(LLess(Local1,DerefOf(Index(TBUF,0))))
 636   {
 637     // Wait up to 200ms for Host Status to get set.
 638
 639     Store(4000,Local0)              // 4000 * 50us = 200ms.
 640
 641     While(LAnd(LNot(And(HSTS,0x80)),Local0))
 642     {
 643       Decrement(Local0)       // Decrement Count.
 644       Stall(50)               // Delay = 50us.
 645     }
 646
 647     If(LNot(Local0))                // Timeout?
 648     {
 649       KILL()                  // Yes.  Kill Communication.
 650       Return(0)               // Return failure.
 651     }
 652
 653     Store(HBDR,Index(TBUF,Local1))  // Place into Buffer.
 654     Store(0x80,HSTS)                // Clear Host Status.
 655     Increment(Local1)
 656   }
 657
 658   // Step 5:  Exit the Method correctly.
 659
 660   If(COMP())
 661   {
 662     Or(HSTS,0xFF,HSTS)              // Clear INUSE_STS and others.
 663     Return(TBUF)                    // Return Success.
 664   }
 665
 666   Return(0)                               // Return Failure.
 667 }
 668
 669
 670 // SMBus Start Check
 671 //      Return: Success = 0
 672 //              Failure = 1
 673
 674 Method(STRT,0,Serialized)
 675 {
 676   OperationRegion(SMPB,PCI_Config,0x20,4)
 677   Field(SMPB,DWordAcc,NoLock,Preserve)
 678   {
 679     ,     5,
 680     SBAR, 11
 681   }
 682
 683   // Define various SMBus IO Mapped Registers.
 684
 685   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 686   Field(SMBI,ByteAcc,NoLock,Preserve)
 687   {
 688     HSTS, 8,        // 0 - Host Status Register
 689         Offset(0x02),
 690         HCON, 8,        // 2 - Host Control
 691         HCOM, 8,        // 3 - Host Command
 692         TXSA, 8,        // 4 - Transmit Slave Address
 693         DAT0, 8,        // 5 - Host Data 0
 694         DAT1, 8,        // 6 - Host Data 1
 695         HBDR, 8,        // 7 - Host Block Data
 696         PECR, 8,        // 8 - Packer Error Check
 697         RXSA, 8,        // 9 - Receive Slave Address
 698         SDAT, 16,       // A - Slave Data
 699   }
 700   // Wait up to 200ms to confirm the SMBus Semaphore has been
 701   // released (In Use Status = 0).  Note that the Sleep time may take
 702   // longer as the This function will yield the Processor such that it
 703   // may perform different tasks during the delay.
 704
 705   Store(200,Local0)                       // 200 * 1ms = 200ms.
 706
 707   While(Local0)
 708   {
 709     If(And(HSTS,0x40))              // In Use Set?
 710     {
 711       Decrement(Local0)       // Yes.  Decrement Count.
 712       Sleep(1)                // Delay = 1ms.
 713       If(LEqual(Local0,0))    // Count = 0?
 714       {
 715         Return(1)       // Return failure.
 716       }
 717     }
 718     Else
 719     {
 720       Store(0,Local0)         // In Use Clear.  Continue.
 721     }
 722   }
 723
 724   // In Use Status = 0 during last read, which will make subsequent
 725   // reads return In Use Status = 1 until software clears it.  All
 726   // software using ICHx SMBus should check this bit before initiating
 727   // any SMBus communication.
 728
 729   // Wait up to 200ms to confirm the Host Interface is
 730   // not processing a command.
 731
 732   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 733
 734   While(Local0)
 735   {
 736     If(And(HSTS,0x01))              // Host Busy Set?
 737     {
 738       Decrement(Local0)       // Decrement Count.
 739       Stall(50)               // Delay = 50us.
 740       If(LEqual(Local0,0))    // Count = 0?
 741       {
 742         KILL()          // Yes.  Kill Communication.
 743       }
 744     }
 745     Else
 746     {
 747       Return(0)
 748     }
 749   }
 750
 751   Return(1)                               // Timeout.  Return failure.
 752 }
 753
 754 // SMBus Completion Check
 755 //      Return: Success = 1
 756 //              Failure = 0
 757
 758 Method(COMP,0,Serialized)
 759 {
 760   OperationRegion(SMPB,PCI_Config,0x20,4)
 761   Field(SMPB,DWordAcc,NoLock,Preserve)
 762   {
 763     ,     5,
 764     SBAR, 11
 765   }
 766
 767   // Define various SMBus IO Mapped Registers.
 768
 769   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 770   Field(SMBI,ByteAcc,NoLock,Preserve)
 771   {
 772     HSTS, 8,        // 0 - Host Status Register
 773         Offset(0x02),
 774         HCON, 8,        // 2 - Host Control
 775         HCOM, 8,        // 3 - Host Command
 776         TXSA, 8,        // 4 - Transmit Slave Address
 777         DAT0, 8,        // 5 - Host Data 0
 778         DAT1, 8,        // 6 - Host Data 1
 779         HBDR, 8,        // 7 - Host Block Data
 780         PECR, 8,        // 8 - Packer Error Check
 781         RXSA, 8,        // 9 - Receive Slave Address
 782         SDAT, 16,       // A - Slave Data
 783   }
 784   // Wait for up to 200ms for the Completion Command
 785   // Status to get set.
 786
 787   Store(4000,Local0)                      // 4000 * 50us = 200ms.
 788
 789   While(Local0)
 790   {
 791     If(And(HSTS,0x02))              // Completion Status Set?
 792     {
 793       Return(1)               // Yes.  We are done.
 794     }
 795     Else
 796     {
 797       Decrement(Local0)       // Decrement Count.
 798       Stall(50)               // Delay 50us.
 799       If(LEqual(Local0,0))    // Count = 0?
 800       {
 801         KILL()          // Yes.  Kill Communication.
 802       }
 803     }
 804   }
 805
 806   Return(0)                               // Timeout.  Return Failure.
 807 }
 808
 809 // SMBus Kill Command
 810
 811 Method(KILL,0,Serialized)
 812 {
 813   OperationRegion(SMPB,PCI_Config,0x20,4)
 814   Field(SMPB,DWordAcc,NoLock,Preserve)
 815   {
 816     ,     5,
 817     SBAR, 11
 818   }
 819
 820   // Define various SMBus IO Mapped Registers.
 821
 822   OperationRegion(SMBI,SystemIO,ShiftLeft(SBAR,5),0x10)
 823   Field(SMBI,ByteAcc,NoLock,Preserve)
 824   {
 825     HSTS, 8,        // 0 - Host Status Register
 826         Offset(0x02),
 827         HCON, 8,        // 2 - Host Control
 828         HCOM, 8,        // 3 - Host Command
 829         TXSA, 8,        // 4 - Transmit Slave Address
 830         DAT0, 8,        // 5 - Host Data 0
 831         DAT1, 8,        // 6 - Host Data 1
 832         HBDR, 8,        // 7 - Host Block Data
 833         PECR, 8,        // 8 - Packer Error Check
 834         RXSA, 8,        // 9 - Receive Slave Address
 835         SDAT, 16,       // A - Slave Data
 836   }
 837   Or(HCON,0x02,HCON)                      // Yes.  Send Kill command.
 838   Or(HSTS,0xFF,HSTS)                      // Clear all status.
 839 }