Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/ApIst.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Silvermont Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2006 - 2014, Intel Corporation
   8
   9   This program and the accompanying materials are licensed and made available under
  10   the terms and conditions of the BSD License that accompanies this distribution.
  11   The full text of the license may be found at
  12   http://opensource.org/licenses/bsd-license.php.
  13
  14   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17
  18  Filename:      APIST.ASL
  19
  20  Revision:      Refer to Readme
  21
  22  Date:          Refer to Readme
  23
  24 --------------------------------------------------------------------------------
  25 -------------------------------------------------------------------------------
  26
  27  This Processor Power Management BIOS Source Code is furnished under license
  28  and may only be used or copied in accordance with the terms of the license.
  29  The information in this document is furnished for informational use only, is
  30  subject to change without notice, and should not be construed as a commitment
  31  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  32  for any errors or inaccuracies that may appear in this document or any
  33  software that may be provided in association with this document.
  34
  35  Except as permitted by such license, no part of this document may be
  36  reproduced, stored in a retrieval system, or transmitted in any form or by
  37  any means without the express written consent of Intel Corporation.
  38
  39  WARNING: You are authorized and licensed to install and use this BIOS code
  40  ONLY on an IST PC. This utility may damage any system that does not
  41  meet these requirements.
  42
  43         An IST PC is a computer which
  44         (1) Is capable of seamlessly and automatically transitioning among
  45         multiple performance states (potentially operating at different
  46         efficiency ratings) based upon power source changes, END user
  47         preference, processor performance demand, and thermal conditions; and
  48         (2) Includes an Intel Pentium II processors, Intel Pentium III
  49         processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  50         Processor-M, Intel Pentium M Processor, or any other future Intel
  51         processors that incorporates the capability to transition between
  52         different performance states by altering some, or any combination of,
  53         the following processor attributes: core voltage, core frequency, bus
  54         frequency, number of processor cores available, or any other attribute
  55         that changes the efficiency (instructions/unit time-power) at which the
  56         processor operates.
  57
  58 -------------------------------------------------------------------------------
  59 -------------------------------------------------------------------------------
  60
  61 NOTES:
  62         (1) <TODO> - IF the trap range and port definitions do not match those
  63         specified by this reference code, this file must be modified IAW the
  64         individual implmentation.
  65
  66 --------------------------------------------------------------------------------
  67 ------------------------------------------------------------------------------*/
  68
  69
  70 DefinitionBlock (
  71         "APIST.aml",
  72         "SSDT",
  73         1,
  74         "PmRef",
  75         "ApIst",
  76         0x3000
  77         )
  78 {
  79         External(\_PR.CPU0._PSS, MethodObj)
  80         External(\_PR.CPU0._PCT, MethodObj)
  81         External(\_PR.CPU0._PPC, IntObj)
  82         External(\_PR.CPU0._PSD, MethodObj)
  83         External(\_PR.CPU1, DeviceObj)
  84         External(\_PR.CPU2, DeviceObj)
  85         External(\_PR.CPU3, DeviceObj)
  86         External (CFGD)
  87         External (PDC0)
  88
  89         Scope(\_PR.CPU1)
  90         {
  91                 Method(_PPC,0)
  92                 {
  93                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
  94                 }
  95
  96                 Method(_PCT,0)
  97                 {
  98                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
  99                 }
 100
 101                 Method(_PSS,0)
 102                 {
 103                         //Return the same table as CPU0 for CMP cases.
 104                         Return(\_PR.CPU0._PSS)
 105                 }
 106
 107                 // The _PSD object provides information to the OSPM related
 108                 // to P-State coordination between processors in a multi-processor
 109                 // configurations.
 110                 //
 111                 Method(_PSD,0)
 112                 {
 113                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 114                 }
 115         }
 116
 117         Scope(\_PR.CPU2)
 118         {
 119                 Method(_PPC,0)
 120                 {
 121                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
 122                 }
 123
 124                 Method(_PCT,0)
 125                 {
 126                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
 127                 }
 128
 129                 Method(_PSS,0)
 130                 {
 131                         //Return the same table as CPU0 for CMP cases.
 132                         Return(\_PR.CPU0._PSS)
 133                 }
 134
 135                 // The _PSD object provides information to the OSPM related
 136                 // to P-State coordination between processors in a multi-processor
 137                 // configurations.
 138                 //
 139                 Method(_PSD,0)
 140                 {
 141                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 142                 }
 143         }
 144
 145         Scope(\_PR.CPU3)
 146         {
 147                 Method(_PPC,0)
 148                 {
 149                         Return(\_PR.CPU0._PPC)  // Return P0 _PPC value.
 150                 }
 151
 152                 Method(_PCT,0)
 153                 {
 154                         Return(\_PR.CPU0._PCT)  // Return P0 _PCT.
 155                 }
 156
 157                 Method(_PSS,0)
 158                 {
 159                         //Return the same table as CPU0 for CMP cases.
 160                         Return(\_PR.CPU0._PSS)
 161                 }
 162
 163                 // The _PSD object provides information to the OSPM related
 164                 // to P-State coordination between processors in a multi-processor
 165                 // configurations.
 166                 //
 167                 Method(_PSD,0)
 168                 {
 169                         Return(\_PR.CPU0._PSD)  // Return P0 _PSD.
 170                 }
 171         }
 172 } // End of Definition Block