Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/CpuPm.asl

   1 /*-----------------------------------------------------------------------------
   2
   3
   4  Intel Silvermont Processor Power Management BIOS Reference Code
   5
   6  Copyright (c) 2006 - 2014, Intel Corporation
   7
   8   This program and the accompanying materials are licensed and made available under
   9   the terms and conditions of the BSD License that accompanies this distribution.
  10   The full text of the license may be found at
  11   http://opensource.org/licenses/bsd-license.php.
  12
  13   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  14   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  15
  16
  17  Filename:    CPUPM.ASL
  18
  19  Revision:    Refer to Readme
  20
  21  Date:        Refer to Readme
  22 -------------------------------------------------------------------------------
  23
  24  This Processor Power Management BIOS Source Code is furnished under license
  25  and may only be used or copied in accordance with the terms of the license.
  26  The information in this document is furnished for informational use only, is
  27  subject to change without notice, and should not be construed as a commitment
  28  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  29  for any errors or inaccuracies that may appear in this document or any
  30  software that may be provided in association with this document.
  31
  32  Except as permitted by such license, no part of this document may be
  33  reproduced, stored in a retrieval system, or transmitted in any form or by
  34  any means without the express written consent of Intel Corporation.
  35
  36  WARNING: You are authorized and licensed to install and use this BIOS code
  37  ONLY on an IST PC. This utility may damage any system that does not
  38  meet these requirements.
  39
  40     An IST PC is a computer which
  41     (1) Is capable of seamlessly and automatically transitioning among
  42     multiple performance states (potentially operating at different
  43     efficiency ratings) based upon power source changes, END user
  44     preference, processor performance demand, and thermal conditions; and
  45     (2) Includes an Intel Pentium II processors, Intel Pentium III
  46     processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  47     Processor-M, Intel Pentium M Processor, or any other future Intel
  48     processors that incorporates the capability to transition between
  49     different performance states by altering some, or any combination of,
  50     the following processor attributes: core voltage, core frequency, bus
  51     frequency, number of processor cores available, or any other attribute
  52     that changes the efficiency (instructions/unit time-power) at which the
  53     processor operates.
  54 -------------------------------------------------------------------------------
  55
  56 NOTES:
  57     (1) <TODO> - Except for the SSDT package, the objects in this ASL code
  58     may be moved to the DSDT. It is kept separate in this reference package
  59     for ease of distribution only.
  60 ------------------------------------------------------------------------------*/
  61
  62 DefinitionBlock (
  63     "CPUPM.aml",
  64     "SSDT",
  65     0x01,
  66     "PmRef",
  67     "CpuPm",
  68     0x3000
  69     )
  70 {
  71     External(\_PR.CPU0, DeviceObj)
  72     External(\_PR.CPU1, DeviceObj)
  73     External(\_PR.CPU2, DeviceObj)
  74     External(\_PR.CPU3, DeviceObj)
  75     External(SMIF)
  76
  77   Scope(\)
  78   {
  79
  80       // Package of pointers to SSDT's
  81       //
  82       // First column is SSDT name, used for debug only.
  83       // (First column must be EXACTLY eight characters.)
  84       // Second column is physical address.
  85       // Third column is table length.
  86       //
  87       // IF modifying this file, see warnings listed in ppminit.asm.
  88       //
  89       Name(SSDT,Package()
  90       {
  91           "CPU0IST ", 0x80000000, 0x80000000,
  92           "APIST   ", 0x80000000, 0x80000000,
  93           "CPU0CST ", 0x80000000, 0x80000000,
  94           "APCST   ", 0x80000000, 0x80000000
  95       })
  96
  97       //
  98       // Note:  See PpmBiosInit in PPMINIT.ASM for a definition of
  99       // the PpmFlags mirrored in CFGD.
 100       //
 101       Name(CFGD, 0x80000000)
 102
 103       Name(\PDC0,0x80000000)    // CPU0 _PDC Flags.
 104       Name(\PDC1,0x80000000)    // CPU1 _PDC Flags.
 105       Name(\PDC2,0x80000000)    // CPU2 _PDC Flags.
 106       Name(\PDC3,0x80000000)    // CPU3 _PDC Flags.
 107       Name(\SDTL,0x00)          // Loaded SSDT Flags.
 108   }
 109
 110   Scope(\_PR.CPU0)
 111   {
 112       //
 113       // Define handles for opregions (used by load.)
 114       //
 115       Name(HI0,0)        // Handle to CPU0IST
 116       Name(HC0,0)        // Handle to CPU0CST
 117
 118       Method(_PDC,1)
 119       {
 120           //
 121           // Check and extract the _PDC information.
 122           //
 123           Store(CPDC(Arg0), Local0)
 124           //
 125           // Save the capability information and load tables as needed.
 126           //
 127           GCAP(Local0)
 128           //
 129           // Return status.
 130           //
 131           //Return (Local0)
 132       }
 133
 134       Method(_OSC, 4)
 135       {
 136           //
 137           // Check and extract the _OSC information.
 138           //
 139           Store(COSC(Arg0, Arg1, Arg2, Arg3), Local0)
 140           //
 141           // Save the capability information and load tables as needed.
 142           //
 143           GCAP(Local0)
 144           //
 145           // Return status.
 146           //
 147           Return (Local0)
 148       }
 149
 150       //
 151       // Implement a generic Method to check _PDC information which may be called
 152       // by any of the processor scopes.  (The use of _PDC is deprecated in ACPI 3.
 153       // in favor of _OSC. However, for backwards compatibility, _PDC may be
 154       // implemented using _OSC as follows:)
 155       //
 156       Method(CPDC,1)
 157       {
 158           CreateDwordField (Arg0, 0, REVS)
 159           CreateDwordField (Arg0, 4, SIZE)
 160
 161           //
 162           // Local0 = Number of bytes for Arg0
 163           //
 164           Store (SizeOf (Arg0), Local0)
 165
 166           //
 167           // Local1 = Number of Capabilities bytes in Arg0
 168           //
 169           Store (Subtract (Local0, 8), Local1)
 170
 171           //
 172           // TEMP = Temporary field holding Capability DWORDs
 173           //
 174           CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)
 175
 176           //
 177           // Create the Status (STAT) buffer with the first DWORD = 0
 178           // This is required as per ACPI 3.0 Spec which says the
 179           // first DWORD is used to return errors defined by _OSC.
 180           //
 181           Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})
 182
 183           //
 184           // Concatenate the _PDC capabilities bytes to the STS0 Buffer
 185           // and store them in a local variable for calling OSC
 186           //
 187           Concatenate (STS0, TEMP, Local2)
 188
 189           Return(COSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2))
 190       }
 191
 192       //
 193       // Implement a generic Method to check _OSC information which may be called
 194       // by any of the processor scopes.
 195       //
 196       Method(COSC, 4)
 197       {
 198           //
 199           // Point to Status DWORD in the Arg3 buffer (STATUS)
 200           //
 201           CreateDWordField(Arg3, 0, STS0)
 202           //
 203           // Point to Caps DWORDs of the Arg3 buffer (CAPABILITIES)
 204           //
 205           CreateDwordField(Arg3, 4, CAP0)
 206
 207           //
 208           // _OSC needs to validate the UUID and Revision.
 209           //
 210           // IF Unrecognized UUID
 211           //    Return Unrecognized UUID _OSC Failure
 212           // IF Unsupported Revision
 213           //    Return Unsupported Revision _OSC Failure
 214           //
 215           //    STS0[0] = Reserved
 216           //    STS0[1] = _OSC Failure
 217           //    STS0[2] = Unrecognized UUID
 218           //    STS0[3] = Unsupported Revision
 219           //    STS0[4] = Capabilities masked
 220           //
 221           // Note:  The comparison method used is necessary due to
 222           // limitations of certain OSes which cannot perform direct
 223           // buffer comparisons.
 224           //
 225           // Create a set of "Input" UUID fields.
 226           //
 227           CreateDwordField(Arg0, 0x0, IID0)
 228           CreateDwordField(Arg0, 0x4, IID1)
 229           CreateDwordField(Arg0, 0x8, IID2)
 230           CreateDwordField(Arg0, 0xC, IID3)
 231           //
 232           // Create a set of "Expected" UUID fields.
 233           //
 234           Name(UID0, ToUUID("4077A616-290C-47BE-9EBD-D87058713953"))
 235           CreateDwordField(UID0, 0x0, EID0)
 236           CreateDwordField(UID0, 0x4, EID1)
 237           CreateDwordField(UID0, 0x8, EID2)
 238           CreateDwordField(UID0, 0xC, EID3)
 239           //
 240           // Verify the input UUID matches the expected UUID.
 241           //
 242           If(LNot(LAnd(LAnd(LEqual(IID0, EID0),LEqual(IID1, EID1)),LAnd(LEqual(IID2, EID2),LEqual(IID3, EID3)))))
 243           {
 244               //
 245               // Return Unrecognized UUID _OSC Failure
 246               //
 247               Store (0x6, STS0)
 248               Return (Arg3)
 249           }
 250
 251           If(LNot(LEqual(Arg1,1)))
 252           {
 253               //
 254               // Return Unsupported Revision _OSC Failure
 255               //
 256               Store (0xA, STS0)
 257               Return (Arg3)
 258           }
 259
 260           Return (Arg3)
 261       }
 262
 263       //
 264       // Get the capability information and load appropriate tables as needed.
 265       //
 266       Method(GCAP, 1)
 267       {
 268
 269           // Point to Status DWORD in the Arg0 buffer (STATUS)
 270           CreateDWordField(Arg0, 0, STS0)
 271
 272           // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
 273           CreateDwordField(Arg0, 4, CAP0)
 274
 275           //
 276           // If the UUID was unrecognized or the _OSC revision was unsupported,
 277           // return without updating capabilities.
 278           //
 279           If(LOr(LEqual(STS0,0x6),LEqual(STS0,0xA)))
 280           {
 281               Return()
 282           }
 283
 284           //
 285           // Check if this is a query (BIT0 of Status = 1).
 286           // If so, mask off the bits we support and return.
 287           //
 288           if (And(STS0, 1))
 289           {
 290               And(CAP0, 0xBFF, CAP0)
 291               Return()
 292           }
 293
 294           //
 295           // Store result of PDC. (We clear out the MSB, which was just
 296           // used as a placeholder for the compiler; and then "OR" the
 297           // value in case we get multiple calls, each of which only
 298           // reports partial support.)
 299           //
 300           Or(And(PDC0, 0x7FFFFFFF), CAP0, PDC0)
 301
 302           //
 303           // Check IF the IST SSDTs should be loaded.
 304           //
 305           //   CFGD[0] = GV3 Capable/Enabled
 306           //
 307           If(And(CFGD,0x01))
 308           {
 309               //
 310               // Load the IST SSDTs if:
 311               //   (1) CMP capable and enabled.
 312               //   (2) Driver supports P-States in MP configurations
 313               //   (3) Driver supports direct HW P-State control
 314               //   (4) SSDT is not already loaded
 315               //
 316               //   CFGD[24] = Two or more cores enabled
 317               //   PDCx[3]  = OS supports C1 and P-states in MP systems
 318               //   PDCx[0]  = OS supports direct access of the perf MSR
 319               //   SDTL[0]  = CPU0 IST SSDT Loaded
 320               //
 321               If(LAnd(LAnd(And(CFGD,0x01000000),LEqual(And(PDC0, 0x0009), 0x0009)),LNot(And(SDTL,0x01))))
 322               {
 323                   //
 324                   // Flag the IST SSDT as loaded for CPU0
 325                   //
 326                   Or(SDTL, 0x01, SDTL)
 327
 328                   OperationRegion(IST0,SystemMemory,DeRefOf(Index(SSDT,1)),DeRefOf(Index(SSDT,2)))
 329                   Load(IST0, HI0)    // Dynamically load the CPU0IST SSDT
 330               }
 331           }
 332
 333           //
 334           // Check IF the CST SSDTs should be loaded.
 335           //
 336           //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
 337           //
 338           If(And(CFGD,0x82))
 339           {
 340               //
 341               // Load the CST SSDTs if:
 342               //   (1) CMP capable/enabled
 343               //   (2) Driver supports multi-processor configurations
 344               //   (3) CPU0 CST ISDT is not already loaded
 345               //
 346               //   CFGD[24] = Two or more cores enabled
 347               //   PDCx[3]  = OS supports C1 and P-states in MP systems
 348               //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
 349               //   SDTL[1]  = CPU0 CST SSDT Loaded
 350               //
 351               If(LAnd(LAnd(And(CFGD,0x01000000),And(PDC0,0x0018)),LNot(And(SDTL,0x02))))
 352               {
 353                   //
 354                   // Flag the CST SSDT as loaded for CPU0
 355                   //
 356                   Or(SDTL, 0x02, SDTL)
 357
 358                   OperationRegion(CST0,SystemMemory,DeRefOf(Index(SSDT,7)),DeRefOf(Index(SSDT,8)))
 359                   Load(CST0, HC0)    // Dynamically load the CPU0CST SSDT
 360               }
 361           }
 362
 363           Return ()
 364       }
 365   }
 366
 367
 368   Scope(\_PR.CPU1)
 369   {
 370       //
 371       // Define handles for opregions (used by load.)
 372       //
 373       Name(HI1,0)        // Handle to APIST
 374       Name(HC1,0)        // Handle to APCST
 375
 376       Method(_PDC,1)
 377       {
 378           //
 379           // Refer to \_PR.CPU0._PDC for description.
 380           //
 381           Store(\_PR.CPU0.CPDC(Arg0), Local0)
 382           GCAP(Local0)
 383           //Return (Local0)
 384       }
 385
 386       Method(_OSC, 4)
 387       {
 388           //
 389           // Refer to \_PR.CPU0._OSC for description.
 390           //
 391           Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
 392           GCAP(Local0)
 393           Return (Local0)
 394       }
 395
 396       //
 397       // Get the capability information and load appropriate tables as needed.
 398       //
 399       Method(GCAP, 1)
 400       {
 401           //
 402           // Point to Status DWORD in the Arg0 buffer (STATUS)
 403           //
 404           CreateDWordField(Arg0, 0, STS1)
 405           //
 406           // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
 407           //
 408           CreateDwordField(Arg0, 4, CAP1)
 409           //
 410           // If the UUID was unrecognized or the _OSC revision was unsupported,
 411           // return without updating capabilities.
 412           //
 413           If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
 414           {
 415               Return()
 416           }
 417
 418           //
 419           // Check if this is a query (BIT0 of Status = 1).
 420           // If so, mask off the bits we support and return.
 421           //
 422           if (And(STS1, 1))
 423           {
 424               And(CAP1, 0xBFF, CAP1)
 425               Return()
 426           }
 427
 428           //
 429           // Store result of PDC. (We clear out the MSB, which was just
 430           // used as a placeholder for the compiler; and then "OR" the
 431           // value in case we get multiple calls, each of which only
 432           // reports partial support.)
 433           //
 434           Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
 435
 436           //
 437           // Attempt to dynamically load the IST SSDTs if:
 438           //   (1) Driver supports P-States in MP configurations
 439           //   (2) Driver supports direct HW P-State control
 440           //
 441           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 442           //   PDCx[0]  = OS supports direct access of the perf MSR
 443           //
 444           If(LEqual(And(PDC0, 0x0009), 0x0009))
 445           {
 446               APPT()
 447           }
 448
 449           //
 450           // Load the CST SSDTs if:
 451           //   (1) Driver supports multi-processor configurations
 452           //
 453           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 454           //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
 455           //
 456           If(And(PDC0,0x0018))
 457           {
 458               APCT()
 459           }
 460
 461           Return()
 462       }
 463
 464       //
 465       // Dynamically load the CST SSDTs if:
 466       //   (1) C-States are enabled
 467       //   (2) SSDT is not already loaded
 468       //
 469       //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
 470       //   SDTL[5]   = AP CST SSDT Loaded
 471       //
 472       Method(APCT,0)
 473       {
 474           If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
 475           {
 476               //
 477               // Flag the CST SSDT as loaded for the AP's
 478               //
 479               Or(SDTL, 0x20, SDTL)
 480               //
 481               // Dynamically load the APCST SSDT
 482               //
 483               OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
 484               Load(CST1, HC1)
 485           }
 486       }
 487
 488       //
 489       // Dynamically load the IST SSDTs if:
 490       //   (1) If GV3 capable and enabled
 491       //   (2) SSDT is not already loaded
 492       //
 493       //   CFGD[0] = GV3 Capable/Enabled
 494       //   SDTL[4] = AP IST SSDT Loaded
 495       //
 496       Method(APPT,0)
 497       {
 498           If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
 499           {
 500               //
 501               // Flag the IST SSDT as loaded for CPU0
 502               //
 503               Or(SDTL, 0x10, SDTL)
 504
 505               OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
 506               Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT
 507           }
 508       }
 509   }    // End CPU1
 510
 511   Scope(\_PR.CPU2)
 512   {
 513       //
 514       // Define handles for opregions (used by load.)
 515       //
 516       Name(HI1,0)        // Handle to APIST
 517       Name(HC1,0)        // Handle to APCST
 518
 519       Method(_PDC,1)
 520       {
 521           //
 522           // Refer to \_PR.CPU0._PDC for description.
 523           //
 524           Store(\_PR.CPU0.CPDC(Arg0), Local0)
 525           GCAP(Local0)
 526           //Return (Local0)
 527       }
 528
 529       Method(_OSC, 4)
 530       {
 531           //
 532           // Refer to \_PR.CPU0._OSC for description.
 533           //
 534           Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
 535           GCAP(Local0)
 536           Return (Local0)
 537       }
 538
 539       //
 540       // Get the capability information and load appropriate tables as needed.
 541       //
 542       Method(GCAP, 1)
 543       {
 544           //
 545           // Point to Status DWORD in the Arg0 buffer (STATUS)
 546           //
 547           CreateDWordField(Arg0, 0, STS1)
 548           //
 549           // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
 550           //
 551           CreateDwordField(Arg0, 4, CAP1)
 552           //
 553           // If the UUID was unrecognized or the _OSC revision was unsupported,
 554           // return without updating capabilities.
 555           //
 556           If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
 557           {
 558               Return()
 559           }
 560
 561           //
 562           // Check if this is a query (BIT0 of Status = 1).
 563           // If so, mask off the bits we support and return.
 564           //
 565           if (And(STS1, 1))
 566           {
 567               And(CAP1, 0xBFF, CAP1)
 568               Return()
 569           }
 570
 571           //
 572           // Store result of PDC. (We clear out the MSB, which was just
 573           // used as a placeholder for the compiler; and then "OR" the
 574           // value in case we get multiple calls, each of which only
 575           // reports partial support.)
 576           //
 577           Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
 578
 579           //
 580           // Attempt to dynamically load the IST SSDTs if:
 581           //   (1) Driver supports P-States in MP configurations
 582           //   (2) Driver supports direct HW P-State control
 583           //
 584           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 585           //   PDCx[0]  = OS supports direct access of the perf MSR
 586           //
 587           If(LEqual(And(PDC0, 0x0009), 0x0009))
 588           {
 589               APPT()
 590           }
 591
 592           //
 593           // Load the CST SSDTs if:
 594           //   (1) Driver supports multi-processor configurations
 595           //
 596           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 597           //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
 598           //
 599           If(And(PDC0,0x0018))
 600           {
 601               APCT()
 602           }
 603
 604           Return()
 605       }
 606
 607       //
 608       // Dynamically load the CST SSDTs if:
 609       //   (1) C-States are enabled
 610       //   (2) SSDT is not already loaded
 611       //
 612       //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
 613       //   SDTL[5]   = AP CST SSDT Loaded
 614       //
 615       Method(APCT,0)
 616       {
 617           If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
 618           {
 619               //
 620               // Flag the CST SSDT as loaded for the AP's
 621               //
 622               Or(SDTL, 0x20, SDTL)
 623               //
 624               // Dynamically load the APCST SSDT
 625               //
 626               OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
 627               Load(CST1, HC1)
 628           }
 629       }
 630
 631       //
 632       // Dynamically load the IST SSDTs if:
 633       //   (1) If GV3 capable and enabled
 634       //   (2) SSDT is not already loaded
 635       //
 636       //   CFGD[0] = GV3 Capable/Enabled
 637       //   SDTL[4] = AP IST SSDT Loaded
 638       //
 639       Method(APPT,0)
 640       {
 641           If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
 642           {
 643               //
 644               // Flag the IST SSDT as loaded for CPU0
 645               //
 646               Or(SDTL, 0x10, SDTL)
 647
 648               OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
 649               Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT
 650           }
 651       }
 652   }    // End CPU1
 653
 654   Scope(\_PR.CPU3)
 655   {
 656       //
 657       // Define handles for opregions (used by load.)
 658       //
 659       Name(HI1,0)        // Handle to APIST
 660       Name(HC1,0)        // Handle to APCST
 661
 662       Method(_PDC,1)
 663       {
 664           //
 665           // Refer to \_PR.CPU0._PDC for description.
 666           //
 667           Store(\_PR.CPU0.CPDC(Arg0), Local0)
 668           GCAP(Local0)
 669           //Return (Local0)
 670       }
 671
 672       Method(_OSC, 4)
 673       {
 674           //
 675           // Refer to \_PR.CPU0._OSC for description.
 676           //
 677           Store(\_PR.CPU0.COSC(Arg0, Arg1, Arg2, Arg3), Local0)
 678           GCAP(Local0)
 679           Return (Local0)
 680       }
 681
 682       //
 683       // Get the capability information and load appropriate tables as needed.
 684       //
 685       Method(GCAP, 1)
 686       {
 687           //
 688           // Point to Status DWORD in the Arg0 buffer (STATUS)
 689           //
 690           CreateDWordField(Arg0, 0, STS1)
 691           //
 692           // Point to Caps DWORDs of the Arg0 buffer (CAPABILITIES)
 693           //
 694           CreateDwordField(Arg0, 4, CAP1)
 695           //
 696           // If the UUID was unrecognized or the _OSC revision was unsupported,
 697           // return without updating capabilities.
 698           //
 699           If(LOr(LEqual(STS1,0x6),LEqual(STS1,0xA)))
 700           {
 701               Return()
 702           }
 703
 704           //
 705           // Check if this is a query (BIT0 of Status = 1).
 706           // If so, mask off the bits we support and return.
 707           //
 708           if (And(STS1, 1))
 709           {
 710               And(CAP1, 0xBFF, CAP1)
 711               Return()
 712           }
 713
 714           //
 715           // Store result of PDC. (We clear out the MSB, which was just
 716           // used as a placeholder for the compiler; and then "OR" the
 717           // value in case we get multiple calls, each of which only
 718           // reports partial support.)
 719           //
 720           Or(And(PDC1, 0x7FFFFFFF), CAP1, PDC1)
 721
 722           //
 723           // Attempt to dynamically load the IST SSDTs if:
 724           //   (1) Driver supports P-States in MP configurations
 725           //   (2) Driver supports direct HW P-State control
 726           //
 727           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 728           //   PDCx[0]  = OS supports direct access of the perf MSR
 729           //
 730           If(LEqual(And(PDC0, 0x0009), 0x0009))
 731           {
 732               APPT()
 733           }
 734
 735           //
 736           // Load the CST SSDTs if:
 737           //   (1) Driver supports multi-processor configurations
 738           //
 739           //   PDCx[3]  = OS supports C1 and P-states in MP systems
 740           //   PDCx[4]  = OS supports ind. C2/C3 in MP systems
 741           //
 742           If(And(PDC0,0x0018))
 743           {
 744               APCT()
 745           }
 746
 747           Return()
 748       }
 749
 750       //
 751       // Dynamically load the CST SSDTs if:
 752       //   (1) C-States are enabled
 753       //   (2) SSDT is not already loaded
 754       //
 755       //   CFGD[11,7,2,1] = C6, C4, C1E, C1 Capable/Enabled
 756       //   SDTL[5]   = AP CST SSDT Loaded
 757       //
 758       Method(APCT,0)
 759       {
 760           If(LAnd(And(CFGD,0x82),LNot(And(SDTL,0x20))))
 761           {
 762               //
 763               // Flag the CST SSDT as loaded for the AP's
 764               //
 765               Or(SDTL, 0x20, SDTL)
 766               //
 767               // Dynamically load the APCST SSDT
 768               //
 769               OperationRegion(CST1,SystemMemory,DeRefOf(Index(SSDT,10)),DeRefOf(Index(SSDT,11)))
 770               Load(CST1, HC1)
 771           }
 772       }
 773
 774       //
 775       // Dynamically load the IST SSDTs if:
 776       //   (1) If GV3 capable and enabled
 777       //   (2) SSDT is not already loaded
 778       //
 779       //   CFGD[0] = GV3 Capable/Enabled
 780       //   SDTL[4] = AP IST SSDT Loaded
 781       //
 782       Method(APPT,0)
 783       {
 784           If(LAnd(And(CFGD,0x01),LNot(And(SDTL,0x10))))
 785           {
 786               //
 787               // Flag the IST SSDT as loaded for CPU0
 788               //
 789               Or(SDTL, 0x10, SDTL)
 790
 791               OperationRegion(IST1,SystemMemory,DeRefOf(Index(SSDT,4)),DeRefOf(Index(SSDT,5)))
 792               Load(IST1, HI1)    // Dynamically load the CPU1IST SSDT
 793           }
 794       }
 795   }    // End CPU3
 796 } // End of Definition Block
 797
 798
 799