Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/PlatformBaseAddresses.h

   1 /*++
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15
  16
  17 Module Name:
  18
  19   PlatformBaseAddresses.h
  20
  21 Abstract:
  22
  23
  24
  25 Revision History
  26
  27 ++*/
  28
  29
  30 #ifndef _PLATFORM_BASE_ADDRESSES_H
  31 #define _PLATFORM_BASE_ADDRESSES_H
  32
  33 //
  34 // Define some fixed platform device location information
  35 //
  36
  37 //
  38 // Define platform base
  39 //
  40
  41 //
  42 // SIO
  43 //
  44 #define SIO_BASE_ADDRESS                  0x0680
  45 #define SIO_MONITORING_BASE_ADDRESS       0x0290
  46 #define SIO_BASE_MASK                     0xFFF0
  47 #define WINDBOND_ECIR_BASE_ADDRESS        0x0810
  48 #define SIO_MAILBOX_BASE_ADDRESS          0x0360    // Used by EC controller
  49 #define SIO_EC_CHANNEL2                   0x62      // Used by EC controller for offset 0x62 and 0x66
  50
  51
  52 //
  53 // South Cluster
  54 //
  55 #define ACPI_BASE_ADDRESS                 0x0400
  56 #define GPIO_BASE_ADDRESS                 0x0500
  57 #define SMBUS_BUS_DEV_FUNC                0x1F0300
  58 #define SMBUS_BASE_ADDRESS                0xEFA0     // SMBus IO Base Address
  59 #define SPI_BASE_ADDRESS                  0xFED01000 // SPI Memory Base Address
  60 #define PMC_BASE_ADDRESS                  0xFED03000 // PMC Memory Base Address
  61 #define SMBM_BASE_ADDRESS                 0xFED04000 // SMBus Memory Base Address
  62 #define IO_BASE_ADDRESS                   0xFED0C000 // IO Memory Base Address
  63 #define ILB_BASE_ADDRESS                  0xFED08000 // ILB Memory Base Address
  64 #define HPET_BASE_ADDRESS                 0xFED00000 // HPET Base Address
  65 #define RCBA_BASE_ADDRESS                 0xFED1C000 // Root Complex Base Address
  66 #define MPHY_BASE_ADDRESS                 0xFEF00000 // MPHY Memory Base Address
  67 #define PUNIT_BASE_ADDRESS                0xFED05000 // PUnit Memory Base Address
  68
  69 //
  70 // GPIO GROUP OFFSET
  71 //
  72 #define GPIO_SCORE_OFFSET                 0x0000
  73 #define GPIO_NCORE_OFFSET                 0x1000
  74 #define GPIO_SSUS_OFFSET                  0x2000
  75
  76 //
  77 // MCH/CPU
  78 //
  79 #define DMI_BASE_ADDRESS                  0xFED18000 // 4K, similar to IIO_RCBA // modify from bearlake -- cchew10
  80 #define EP_BASE_ADDRESS                   0xFED19000
  81 #define MC_MMIO_BASE                      0xFED14000 // Base Address for MMIO registers
  82
  83 //
  84 // TPM
  85 //
  86 #define TPM_BASE_ADDRESS                  0xFED40000  // Base address for TPM
  87
  88 //
  89 // Local and I/O APIC addresses.
  90 //
  91 #define IO_APIC_ADDRESS                   0xFEC00000
  92 #define IIO_IOAPIC_ADDRESS                0xFEC90000
  93 #define LOCAL_APIC_ADDRESS                0xFEE00000
  94
  95
  96 #endif
  97
  98