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1 /*++
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved
4
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13
14
15 Module Name:
16
17 PchCommonDefinitions.h
18
19 Abstract:
20
21 This header file provides common definitions for PCH
22
23 --*/
24 #ifndef _PCH_COMMON_DEFINITIONS_H_
25 #define _PCH_COMMON_DEFINITIONS_H_
26
27 //
28 // MMIO access macros
29 //
30 #define PchMmioAddress(BaseAddr, Register) ((UINTN) BaseAddr + (UINTN) (Register))
31
32 //
33 // 32 bit MMIO access
34 //
35 #define PchMmio32Ptr(BaseAddr, Register) ((volatile UINT32 *) PchMmioAddress (BaseAddr, Register))
36
37 #define PchMmio32(BaseAddr, Register) *PchMmio32Ptr (BaseAddr, Register)
38
39 #define PchMmio32Or(BaseAddr, Register, OrData) \
40 PchMmio32 (BaseAddr, Register) = (UINT32) \
41 (PchMmio32 (BaseAddr, Register) | (UINT32) (OrData))
42
43 #define PchMmio32And(BaseAddr, Register, AndData) \
44 PchMmio32 (BaseAddr, Register) = (UINT32) \
45 (PchMmio32 (BaseAddr, Register) & (UINT32) (AndData))
46
47 #define PchMmio32AndThenOr(BaseAddr, Register, AndData, OrData) \
48 PchMmio32 (BaseAddr, Register) = (UINT32) \
49 ((PchMmio32 (BaseAddr, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
50
51 //
52 // 16 bit MMIO access
53 //
54 #define PchMmio16Ptr(BaseAddr, Register) ((volatile UINT16 *) PchMmioAddress (BaseAddr, Register))
55
56 #define PchMmio16(BaseAddr, Register) *PchMmio16Ptr (BaseAddr, Register)
57
58 #define PchMmio16Or(BaseAddr, Register, OrData) \
59 PchMmio16 (BaseAddr, Register) = (UINT16) \
60 (PchMmio16 (BaseAddr, Register) | (UINT16) (OrData))
61
62 #define PchMmio16And(BaseAddr, Register, AndData) \
63 PchMmio16 (BaseAddr, Register) = (UINT16) \
64 (PchMmio16 (BaseAddr, Register) & (UINT16) (AndData))
65
66 #define PchMmio16AndThenOr(BaseAddr, Register, AndData, OrData) \
67 PchMmio16 (BaseAddr, Register) = (UINT16) \
68 ((PchMmio16 (BaseAddr, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
69
70 //
71 // 8 bit MMIO access
72 //
73 #define PchMmio8Ptr(BaseAddr, Register) ((volatile UINT8 *) PchMmioAddress (BaseAddr, Register))
74
75 #define PchMmio8(BaseAddr, Register) *PchMmio8Ptr (BaseAddr, Register)
76
77 #define PchMmio8Or(BaseAddr, Register, OrData) \
78 PchMmio8 (BaseAddr, Register) = (UINT8) \
79 (PchMmio8 (BaseAddr, Register) | (UINT8) (OrData))
80
81 #define PchMmio8And(BaseAddr, Register, AndData) \
82 PchMmio8 (BaseAddr, Register) = (UINT8) \
83 (PchMmio8 (BaseAddr, Register) & (UINT8) (AndData))
84
85 #define PchMmio8AndThenOr(BaseAddr, Register, AndData, OrData) \
86 PchMmio8 (BaseAddr, Register) = (UINT8) \
87 ((PchMmio8 (BaseAddr, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
88
89 //
90 // Memory Mapped PCI Access macros
91 //
92 #define PCH_PCI_EXPRESS_BASE_ADDRESS 0xE0000000
93 //
94 // PCI Device MM Base
95 //
96 #define PchPciDeviceMmBase(Bus, Device, Function) \
97 ( \
98 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
99 (Function << 12) \
100 )
101
102 //
103 // PCI Device MM Address
104 //
105 #define PchPciDeviceMmAddress(Segment, Bus, Device, Function, Register) \
106 ( \
107 (UINTN) PCH_PCI_EXPRESS_BASE_ADDRESS + (UINTN) (Bus << 20) + (UINTN) (Device << 15) + (UINTN) \
108 (Function << 12) + (UINTN) (Register) \
109 )
110
111 //
112 // 32 bit PCI access
113 //
114 #define PchMmPci32Ptr(Segment, Bus, Device, Function, Register) \
115 ((volatile UINT32 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
116
117 #define PchMmPci32(Segment, Bus, Device, Function, Register) *PchMmPci32Ptr (Segment, Bus, Device, Function, Register)
118
119 #define PchMmPci32Or(Segment, Bus, Device, Function, Register, OrData) \
120 PchMmPci32 ( \
121 Segment, \
122 Bus, \
123 Device, \
124 Function, \
125 Register \
126 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) | (UINT32) (OrData))
127
128 #define PchMmPci32And(Segment, Bus, Device, Function, Register, AndData) \
129 PchMmPci32 ( \
130 Segment, \
131 Bus, \
132 Device, \
133 Function, \
134 Register \
135 ) = (UINT32) (PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData))
136
137 #define PchMmPci32AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
138 PchMmPci32 ( \
139 Segment, \
140 Bus, \
141 Device, \
142 Function, \
143 Register \
144 ) = (UINT32) ((PchMmPci32 (Segment, Bus, Device, Function, Register) & (UINT32) (AndData)) | (UINT32) (OrData))
145
146 //
147 // 16 bit PCI access
148 //
149 #define PchMmPci16Ptr(Segment, Bus, Device, Function, Register) \
150 ((volatile UINT16 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
151
152 #define PchMmPci16(Segment, Bus, Device, Function, Register) *PchMmPci16Ptr (Segment, Bus, Device, Function, Register)
153
154 #define PchMmPci16Or(Segment, Bus, Device, Function, Register, OrData) \
155 PchMmPci16 ( \
156 Segment, \
157 Bus, \
158 Device, \
159 Function, \
160 Register \
161 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) | (UINT16) (OrData))
162
163 #define PchMmPci16And(Segment, Bus, Device, Function, Register, AndData) \
164 PchMmPci16 ( \
165 Segment, \
166 Bus, \
167 Device, \
168 Function, \
169 Register \
170 ) = (UINT16) (PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData))
171
172 #define PchMmPci16AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
173 PchMmPci16 ( \
174 Segment, \
175 Bus, \
176 Device, \
177 Function, \
178 Register \
179 ) = (UINT16) ((PchMmPci16 (Segment, Bus, Device, Function, Register) & (UINT16) (AndData)) | (UINT16) (OrData))
180
181 //
182 // 8 bit PCI access
183 //
184 #define PchMmPci8Ptr(Segment, Bus, Device, Function, Register) \
185 ((volatile UINT8 *) PchPciDeviceMmAddress (Segment, Bus, Device, Function, Register))
186
187 #define PchMmPci8(Segment, Bus, Device, Function, Register) *PchMmPci8Ptr (Segment, Bus, Device, Function, Register)
188
189 #define PchMmPci8Or(Segment, Bus, Device, Function, Register, OrData) \
190 PchMmPci8 ( \
191 Segment, \
192 Bus, \
193 Device, \
194 Function, \
195 Register \
196 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) | (UINT8) (OrData))
197
198 #define PchMmPci8And(Segment, Bus, Device, Function, Register, AndData) \
199 PchMmPci8 ( \
200 Segment, \
201 Bus, \
202 Device, \
203 Function, \
204 Register \
205 ) = (UINT8) (PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData))
206
207 #define PchMmPci8AndThenOr(Segment, Bus, Device, Function, Register, AndData, OrData) \
208 PchMmPci8 ( \
209 Segment, \
210 Bus, \
211 Device, \
212 Function, \
213 Register \
214 ) = (UINT8) ((PchMmPci8 (Segment, Bus, Device, Function, Register) & (UINT8) (AndData)) | (UINT8) (OrData))
215
216 #endif