Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/PchPlatformPolicy.h

   1 /**
   2 **/
   3 /**
   4
   5 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   6
   7   This program and the accompanying materials are licensed and made available under
   8   the terms and conditions of the BSD License that accompanies this distribution.
   9   The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15
  16
  17   @file
  18   PchPlatformPolicy.h
  19
  20   @brief
  21   PCH policy PPI produced by a platform driver specifying various
  22   expected PCH settings. This PPI is consumed by the PCH PEI modules.
  23
  24 **/
  25 #ifndef PCH_PLATFORM_POLICY_H_
  26 #define PCH_PLATFORM_POLICY_H_
  27 //
  28 // External include files do NOT need to be explicitly specified in real EDKII
  29 // environment
  30 //
  31
  32
  33 #include "PchRegs.h"
  34
  35 //
  36 #define PCH_PLATFORM_POLICY_PPI_GUID \
  37   { \
  38     0x15344673, 0xd365, 0x4be2, 0x85, 0x13, 0x14, 0x97, 0xcc, 0x7, 0x61, 0x1d \
  39   }
  40
  41 extern EFI_GUID                         gPchPlatformPolicyPpiGuid;
  42
  43 ///
  44 /// Forward reference for ANSI C compatibility
  45 ///
  46 typedef struct _PCH_PLATFORM_POLICY_PPI PCH_PLATFORM_POLICY_PPI;
  47
  48 ///
  49 /// PPI revision number
  50 /// Any backwards compatible changes to this PPI will result in an update in the revision number
  51 /// Major changes will require publication of a new PPI
  52 ///
  53 /// Revision 1:    Original version
  54 ///
  55 #define PCH_PLATFORM_POLICY_PPI_REVISION_1  1
  56 #define PCH_PLATFORM_POLICY_PPI_REVISION_2  2
  57 #define PCH_PLATFORM_POLICY_PPI_REVISION_3  3
  58 #define PCH_PLATFORM_POLICY_PPI_REVISION_4  4
  59 #define PCH_PLATFORM_POLICY_PPI_REVISION_5  5
  60 //
  61 // Generic definitions for device enabling/disabling used by PCH code.
  62 //
  63 #define PCH_DEVICE_ENABLE   1
  64 #define PCH_DEVICE_DISABLE  0
  65
  66 typedef struct {
  67   UINT8  ThermalDataReportEnable  : 1;   // OBSOLETE from Revision 5 !!! DO NOT USE !!!
  68   UINT8  MchTempReadEnable        : 1;
  69   UINT8  PchTempReadEnable        : 1;
  70   UINT8  CpuEnergyReadEnable      : 1;
  71   UINT8  CpuTempReadEnable        : 1;
  72   UINT8  Cpu2TempReadEnable       : 1;
  73   UINT8  TsOnDimmEnable           : 1;
  74   UINT8  Dimm1TempReadEnable      : 1;
  75
  76   UINT8  Dimm2TempReadEnable      : 1;
  77   UINT8  Dimm3TempReadEnable      : 1;
  78   UINT8  Dimm4TempReadEnable      : 1;
  79   UINT8  Rsvdbits                 : 5;
  80 } PCH_THERMAL_REPORT_CONTROL;
  81 //
  82 // ---------------------------- HPET Config -----------------------------
  83 //
  84 typedef struct {
  85   BOOLEAN Enable; /// Determines if enable HPET function
  86   UINT32  Base;   /// The HPET base address
  87 } PCH_HPET_CONFIG;
  88
  89
  90 ///
  91 /// ---------------------------- SATA Config -----------------------------
  92 ///
  93 typedef enum {
  94   PchSataModeIde,
  95   PchSataModeAhci,
  96   PchSataModeRaid,
  97   PchSataModeMax
  98 } PCH_SATA_MODE;
  99
 100 ///
 101 /// ---------------------------- PCI Express Config -----------------------------
 102 ///
 103 typedef enum {
 104   PchPcieAuto,
 105   PchPcieGen1,
 106   PchPcieGen2
 107 } PCH_PCIE_SPEED;
 108
 109 typedef struct {
 110   PCH_PCIE_SPEED  PcieSpeed[PCH_PCIE_MAX_ROOT_PORTS];
 111 } PCH_PCIE_CONFIG;
 112
 113 ///
 114 /// ---------------------------- IO APIC Config -----------------------------
 115 ///
 116 typedef struct {
 117   UINT8 IoApicId;
 118 } PCH_IOAPIC_CONFIG;
 119
 120 ///
 121 /// --------------------- Low Power Input Output Config ------------------------
 122 ///
 123 typedef struct {
 124   UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled
 125   UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled
 126   UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled
 127   UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled
 128   UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled
 129   UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled
 130   UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled
 131   UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled
 132   UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled
 133   UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled
 134   UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled
 135   UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled
 136   UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled
 137   UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled
 138   UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled
 139   UINT8                   Rsvdbits              : 2;
 140 } PEI_PCH_LPSS_CONFIG;
 141
 142 ///
 143 /// ------------ General PCH Platform Policy PPI definition ------------
 144 ///
 145 struct _PCH_PLATFORM_POLICY_PPI {
 146   UINT8                         Revision;
 147   UINT8                         BusNumber;  // Bus Number of the PCH device
 148   UINT32                        SpiBase;    // SPI Base Address.
 149   UINT32                        PmcBase;    // PMC Base Address.
 150   UINT32                        SmbmBase;   // SMB Memory Base Address.
 151   UINT32                        IoBase;     // IO Base Address.
 152   UINT32                        IlbBase;    // Intel Legacy Block Base Address.
 153   UINT32                        PUnitBase;  // PUnit Base Address.
 154   UINT32                        Rcba;       // Root Complex Base Address.
 155   UINT32                        MphyBase;   // MPHY Base Address.
 156   UINT16                        AcpiBase;   // ACPI I/O Base address.
 157   UINT16                        GpioBase;   // GPIO Base address
 158   PCH_HPET_CONFIG               *HpetConfig;
 159   PCH_SATA_MODE                 SataMode;
 160   PCH_PCIE_CONFIG               *PcieConfig;
 161   PCH_IOAPIC_CONFIG             *IoApicConfig;
 162   PEI_PCH_LPSS_CONFIG           *LpssConfig;
 163   BOOLEAN                       EnableRmh;      // Determines if enable USB RMH function
 164   BOOLEAN                       EhciPllCfgEnable;
 165 };
 166
 167 #endif