Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Ppi/Sdhc.h

   1 /**
   2 **/
   3 /**
   4
   5 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
   6
   7   This program and the accompanying materials are licensed and made available under
   8   the terms and conditions of the BSD License that accompanies this distribution.
   9   The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15
  16
  17   @file
  18   Spi.h
  19
  20   @brief
  21   This file defines the EFI SPI PPI which implements the
  22   Intel(R) PCH SPI Host Controller Compatibility Interface.
  23
  24 **/
  25 #ifndef _PEI_SDHC_H_
  26 #define _PEI_SDHC_H_
  27
  28
  29
  30 //
  31 #define PEI_SDHC_PPI_GUID \
  32   {  \
  33     0xf4ef9d7a, 0x98c5, 0x4c1a, 0xb4, 0xd9, 0xd8, 0xd8, 0x72, 0x65, 0xbe, 0xc \
  34   }
  35 typedef struct _PEI_SD_CONTROLLER_PPI PEI_SD_CONTROLLER_PPI;
  36
  37 #define EFI_SD_HOST_IO_PROTOCOL_REVISION_01          0x01
  38
  39 typedef enum {
  40   ResponseNo = 0,
  41   ResponseR1,
  42   ResponseR1b,
  43   ResponseR2,
  44   ResponseR3,
  45   ResponseR4,
  46   ResponseR5,
  47   ResponseR5b,
  48   ResponseR6,
  49   ResponseR7
  50 } RESPONSE_TYPE;
  51
  52 typedef enum {
  53   NoData = 0,
  54   InData,
  55   OutData
  56 } TRANSFER_TYPE;
  57
  58 typedef enum {
  59   Reset_Auto = 0,
  60   Reset_DAT,
  61   Reset_CMD,
  62   Reset_DAT_CMD,
  63   Reset_All
  64 } RESET_TYPE;
  65
  66
  67
  68 typedef enum {
  69   SDMA = 0,
  70   ADMA2,
  71   PIO
  72 } DMA_MOD;
  73
  74 typedef struct {
  75   UINT32  HighSpeedSupport:    1;  //High speed supported
  76   UINT32  V18Support:          1;  //1.8V supported
  77   UINT32  V30Support:          1;  //3.0V supported
  78   UINT32  V33Support:          1;  //3.3V supported
  79   UINT32  Reserved0:           4;
  80   UINT32  BusWidth4:           1;  // 4 bit width
  81   UINT32  BusWidth8:           1;  // 8 bit width
  82   UINT32  Reserved1:           6;
  83   UINT32  SDMASupport:         1;
  84   UINT32  ADMA2Support:        1;
  85   UINT32  DmaMode:             2;
  86   UINT32  Reserved2:           12;
  87   UINT32  BoundarySize;
  88 }HOST_CAPABILITY;
  89
  90
  91 #define PCI_SUBCLASS_SD_HOST_CONTROLLER   0x05
  92 #define PCI_IF_STANDARD_HOST_NO_DMA       0x00
  93 #define PCI_IF_STANDARD_HOST_SUPPORT_DMA  0x01
  94
  95 //
  96 //MMIO Registers definition for MMC/SDIO controller
  97 //
  98 #define  MMIO_DMAADR                     0x00
  99 #define  MMIO_BLKSZ                      0x04
 100 #define  MMIO_BLKCNT                     0x06
 101 #define  MMIO_CMDARG                     0x08
 102 #define  MMIO_XFRMODE                    0x0C
 103 #define  MMIO_SDCMD                      0x0E
 104 #define  MMIO_RESP                       0x10
 105 #define  MMIO_BUFDATA                    0x20
 106 #define  MMIO_PSTATE                     0x24
 107 #define  MMIO_HOSTCTL                    0x28
 108 #define  MMIO_PWRCTL                     0x29
 109 #define  MMIO_BLKGAPCTL                  0x2A
 110 #define  MMIO_WAKECTL                    0x2B
 111 #define  MMIO_CLKCTL                     0x2C
 112 #define  MMIO_TOCTL                      0x2E
 113 #define  MMIO_SWRST                      0x2F
 114 #define  MMIO_NINTSTS                    0x30
 115 #define  MMIO_ERINTSTS                   0x32
 116 #define  MMIO_NINTEN                     0x34
 117 #define  MMIO_ERINTEN                    0x36
 118 #define  MMIO_NINTSIGEN                  0x38
 119 #define  MMIO_ERINTSIGEN                 0x3A
 120 #define  MMIO_AC12ERRSTS                 0x3C
 121 #define  MMIO_HOST_CTL2                  0x3E //hphang <- New in VLV2
 122 #define  MMIO_CAP                        0x40
 123 #define  MMIO_CAP2                       0x44 //hphang <- New in VLV2
 124 #define  MMIO_MCCAP                      0x48
 125 #define  MMIO_FORCEEVENTCMD12ERRSTAT     0x50 //hphang <- New in VLV2
 126 #define  MMIO_FORCEEVENTERRINTSTAT       0x52 //hphang <- New in VLV2
 127 #define  MMIO_ADMAERRSTAT                0x54 //hphang <- New in VLV2
 128 #define  MMIO_ADMASYSADDR                0x58 //hphang <- New in VLV2
 129 #define  MMIO_PRESETVALUE0               0x60 //hphang <- New in VLV2
 130 #define  MMIO_PRESETVALUE1               0x64 //hphang <- New in VLV2
 131 #define  MMIO_PRESETVALUE2               0x68 //hphang <- New in VLV2
 132 #define  MMIO_PRESETVALUE3               0x6C //hphang <- New in VLV2
 133 #define  MMIO_BOOTTIMEOUTCTRL            0x70 //hphang <- New in VLV2
 134 #define  MMIO_DEBUGSEL                   0x74 //hphang <- New in VLV2
 135 #define  MMIO_SHAREDBUS                  0xE0 //hphang <- New in VLV2
 136 #define  MMIO_SPIINTSUP                  0xF0 //hphang <- New in VLV2
 137 #define  MMIO_SLTINTSTS                  0xFC
 138 #define  MMIO_CTRLRVER                   0xFE
 139 #define  MMIO_SRST                       0x1FC
 140
 141 typedef
 142 EFI_STATUS
 143 (EFIAPI *EFI_SD_CONTROLLER_PPI_SEND_COMMAND) (
 144   IN  PEI_SD_CONTROLLER_PPI       *This,
 145   IN   UINT16                     CommandIndex,
 146   IN   UINT32                     Argument,
 147   IN   TRANSFER_TYPE              DataType,
 148   IN   UINT8                      *Buffer, OPTIONAL
 149   IN   UINT32                     BufferSize,
 150   IN   RESPONSE_TYPE              ResponseType,
 151   IN   UINT32                     TimeOut,
 152   OUT  UINT32                     *ResponseData OPTIONAL
 153   );
 154
 155 /*++
 156
 157   Routine Description:
 158     Set max clock frequency of the host, the actual frequency
 159     may not be the same as MaxFrequency. It depends on
 160     the max frequency the host can support, divider, and host
 161     speed mode.
 162
 163   Arguments:
 164     This           - Pointer to EFI_SD_HOST_IO_PROTOCOL
 165     MaxFrequency   - Max frequency in HZ
 166
 167   Returns:
 168     EFI_SUCCESS
 169     EFI_TIMEOUT
 170 --*/
 171 typedef
 172 EFI_STATUS
 173 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY) (
 174   IN  PEI_SD_CONTROLLER_PPI      *This,
 175   IN  UINT32                     MaxFrequency
 176   );
 177
 178 /*++
 179
 180   Routine Description:
 181     Set bus width of the host
 182
 183   Arguments:
 184     This       - Pointer to EFI_SD_HOST_IO_PROTOCOL
 185     BusWidth   - Bus width in 1, 4, 8 bits
 186
 187   Returns:
 188     EFI_SUCCESS
 189     EFI_INVALID_PARAMETER
 190
 191 --*/
 192 typedef
 193 EFI_STATUS
 194 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH) (
 195   IN  PEI_SD_CONTROLLER_PPI      *This,
 196   IN  UINT32                     BusWidth
 197   );
 198
 199 /*++
 200
 201   Routine Description:
 202     Set Host mode in DDR
 203   Arguments:
 204     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 205     SetHostDdrMode   - True for DDR Mode set, false for normal mode
 206
 207   Returns:
 208     EFI_SUCCESS
 209     EFI_INVALID_PARAMETER
 210
 211 --*/
 212 typedef
 213 EFI_STATUS
 214 (EFIAPI *EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE) (
 215   IN  PEI_SD_CONTROLLER_PPI    *This,
 216   IN  UINT32                     DdrMode
 217   );
 218
 219 /*++
 220
 221   Routine Description:
 222     Set voltage which could supported by the host.
 223     Support 0(Power off the host), 1.8V, 3.0V, 3.3V
 224   Arguments:
 225     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 226     Voltage   - Units in 0.1 V
 227
 228   Returns:
 229     EFI_SUCCESS
 230     EFI_INVALID_PARAMETER
 231
 232 --*/
 233 typedef
 234 EFI_STATUS
 235 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE) (
 236   IN  PEI_SD_CONTROLLER_PPI      *This,
 237   IN  UINT32                     Voltage
 238   );
 239
 240 /*++
 241
 242   Routine Description:
 243    Reset the host
 244
 245   Arguments:
 246     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 247     ResetAll  - TRUE to reset all
 248
 249   Returns:
 250     EFI_SUCCESS
 251     EFI_TIMEOUT
 252
 253 --*/
 254 typedef
 255 EFI_STATUS
 256 (EFIAPI *EFI_SD_CONTROLLER_PPI_RESET_SD_HOST) (
 257   IN  PEI_SD_CONTROLLER_PPI      *This,
 258   IN  RESET_TYPE                 ResetType
 259   );
 260
 261 /*++
 262
 263   Routine Description:
 264    Reset the host
 265
 266   Arguments:
 267     This    - Pointer to EFI_SD_HOST_IO_PROTOCOL
 268     Enable  - TRUE to enable, FALSE to disable
 269
 270   Returns:
 271     EFI_SUCCESS
 272     EFI_TIMEOUT
 273
 274 --*/
 275 typedef
 276 EFI_STATUS
 277 (EFIAPI *EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD) (
 278   IN  PEI_SD_CONTROLLER_PPI      *This,
 279   IN  BOOLEAN                    Enable
 280   );
 281
 282 /*++
 283
 284   Routine Description:
 285     Find whether these is a card inserted into the slot. If so
 286     init the host. If not, return EFI_NOT_FOUND.
 287
 288   Arguments:
 289     This      - Pointer to EFI_SD_HOST_IO_PROTOCOL
 290
 291   Returns:
 292     EFI_SUCCESS
 293     EFI_NOT_FOUND
 294
 295 --*/
 296 typedef
 297 EFI_STATUS
 298 (EFIAPI *EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST) (
 299   IN  PEI_SD_CONTROLLER_PPI      *This
 300   );
 301
 302 /*++
 303
 304   Routine Description:
 305    Set the Block length
 306
 307   Arguments:
 308     This        - Pointer to EFI_SD_HOST_IO_PROTOCOL
 309     BlockLength - card supportes block length
 310
 311   Returns:
 312     EFI_SUCCESS
 313     EFI_TIMEOUT
 314
 315 --*/
 316 typedef
 317 EFI_STATUS
 318 (EFIAPI *EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH) (
 319   IN  PEI_SD_CONTROLLER_PPI      *This,
 320   IN  UINT32                     BlockLength
 321   );
 322
 323 /*++
 324
 325   Routine Description:
 326    Set the Block length
 327
 328   Arguments:
 329     This        - Pointer to EFI_SD_HOST_IO_PROTOCOL
 330     BlockLength - card supportes block length
 331
 332   Returns:
 333     EFI_SUCCESS
 334     EFI_TIMEOUT
 335
 336 --*/
 337
 338 typedef EFI_STATUS
 339 (EFIAPI *EFI_SD_CONTROLLER_PPI_SETUP_DEVICE)(
 340   IN  PEI_SD_CONTROLLER_PPI    *This
 341   );
 342
 343 //
 344 // Interface structure for the EFI SD Host I/O Protocol
 345 //
 346 struct _PEI_SD_CONTROLLER_PPI {
 347   UINT32                                           Revision;
 348   HOST_CAPABILITY                                  HostCapability;
 349   EFI_SD_CONTROLLER_PPI_SEND_COMMAND               SendCommand;
 350   EFI_SD_CONTROLLER_PPI_SET_CLOCK_FREQUENCY        SetClockFrequency;
 351   EFI_SD_CONTROLLER_PPI_SET_BUS_WIDTH              SetBusWidth;
 352   EFI_SD_CONTROLLER_PPI_SET_HOST_VOLTAGE           SetHostVoltage;
 353   EFI_SD_HOST_IO_PROTOCOL_SET_HOST_DDR_MODE        SetHostDdrMode;
 354   EFI_SD_CONTROLLER_PPI_RESET_SD_HOST              ResetSdHost;
 355   EFI_SD_CONTROLLER_PPI_ENABLE_AUTO_STOP_CMD       EnableAutoStopCmd;
 356   EFI_SD_CONTROLLER_PPI_DETECT_CARD_AND_INIT_HOST  DetectCardAndInitHost;
 357   EFI_SD_CONTROLLER_PPI_SET_BLOCK_LENGTH           SetBlockLength;
 358   EFI_SD_CONTROLLER_PPI_SETUP_DEVICE               SetupDevice;
 359 };
 360 // Extern the GUID for PPI users.
 361 //
 362 extern EFI_GUID           gPeiSdhcPpiGuid;
 363
 364
 365 #endif