Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/Gpio.h

   1 /*++
   2
   3 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14
  15 Module Name:
  16
  17   Gpio.h
  18
  19 Abstract:
  20
  21 EFI 2.0 PEIM to provide platform specific information to other
  22 modules and to do some platform specific initialization.
  23
  24 --*/
  25
  26 #ifndef _PEI_GPIO_H
  27 #define _PEI_GPIO_H
  28
  29 //#include "Efi.h"
  30 //#include "EfiCommonLib.h"
  31 //#include "Pei.h"
  32 //#include "Numbers.h"
  33
  34 ////
  35 //// GPIO Register Settings for BeaverBridge (FFVS) (Cedarview/Tigerpoint)
  36 ////
  37 //// Field Descriptions:
  38 ////    USE: Defines the pin's usage model:  GPIO (G) or Native (N) mode.
  39 ////    I/O: Defines whether GPIOs are inputs (I) or outputs (O).
  40 ////         (Note:  Only meaningful for pins used as GPIOs.)
  41 ////    LVL: This field gives you the initial value for "output" GPIO's.
  42 ////         (Note: The output level is dependent upon whether the pin is inverted.)
  43 ////    INV: Defines whether Input GPIOs activation level is inverted.
  44 ////         (Note:  Only affects the level sent to the GPE logic and does not
  45 ////         affect the level read through the GPIO registers.)
  46 ////
  47 //// Notes:
  48 ////    1. BoardID is GPIO [8:38:34]
  49 ////
  50 ////Signal         UsedAs               USE     I/O      LVL     INV
  51 ////--------------------------------------------------------------------------
  52 ////GPIO0           Nonfunction       G     O            H       -
  53 ////GPIO1           SMC_RUNTIME_SCI#    G        I           -       I
  54 ////PIRQE#/GPIO2    Nonfunction G   O   H   -
  55 ////PIRQF#/GPIO3    Nonfunction G   O   H   -
  56 ////PIRQG#/GPIO4    Nonfunction G   O   H   -
  57 ////PIRQH#/GPIO5    Nonfunction G   O   H   -
  58 ////GPIO6   unused  G   O   L   -
  59 ////GPIO7   unused  G   O   L   -
  60 ////GPIO8          BOARD ID2    G   I   -   -
  61 ////GPIO9   unused  G   O   L   -
  62 ////GPIO10  SMC_EXTSMI# G   I   -   I
  63 ////GPIO11  Nonfunction G   O   H   -
  64 ////GPIO12  unused  G   O   L   -
  65 ////GPIO13  SMC_WAKE_SCI#   G   I   -   I
  66 ////GPIO14  unused  G   O   L   -
  67 ////GPIO15  unused  G   O   L   -
  68 ////GPIO16  PM_DPRSLPVR N   -   -   -
  69 ////GNT5#/GPIO17    GNT5#   N   -   -   -
  70 ////STPPCI#/GPIO18  PM_STPPCI#  N   -   -   -
  71 ////STPCPU#/GPIO20  PM_STPCPU#  N   -   -   -
  72 ////GPIO22  CRT_RefClk  G   I   -   -
  73 ////GPIO23  unused  G   O   L   -
  74 ////GPIO24  unused  G   O   L   -
  75 ////GPIO25  DMI strap   G   O   L   -
  76 ////GPIO26  unused  G   O   L   -
  77 ////GPIO27  unused  G   O   L   -
  78 ////GPIO28  RF_KILL#    G   O   H   -
  79 ////OC5#/GPIO29 OC  N   -   -   -
  80 ////OC6#/GPIO30 OC  N   -   -   -
  81 ////OC7#/GPIO31 OC  N   -   -   -
  82 ////CLKRUN#/GPIO32  PM_CLKRUN#  N   -   -   -
  83 ////GPIO33  NC  G   O   L   -
  84 ////GPIO34  BOARD ID0   G   I   -   -
  85 ////GPIO36  unused  G   O   L   -
  86 ////GPIO38  BOARD ID1   G   I   -   -
  87 ////GPIO39  unused  G   O   L   -
  88 ////GPIO48  unused  G   O   L   -
  89 ////CPUPWRGD/GPIO49 H_PWRGD N   -   -   -
  90 //
  91 //#define   GPIO_USE_SEL_VAL              0x1FC0FFFF       //GPIO1, 10, 13 is EC signal
  92 //#define   GPIO_USE_SEL2_VAL             0x000100D6
  93 //#define   GPIO_IO_SEL_VAL               0x00402502
  94 //#define   GPIO_IO_SEL2_VAL              0x00000044
  95 //#define   GPIO_LVL_VAL                  0x1800083D
  96 //#define   GPIO_LVL2_VAL                 0x00000000
  97 //#define   GPIO_INV_VAL                  0x00002402
  98 //#define   GPIO_BLNK_VAL                 0x00000000
  99 //#define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
 100
 101 //
 102 // GPIO Register Settings for CedarRock and CedarFalls platforms
 103 //
 104 //      GPIO Register Settings for NB10_CRB
 105 //---------------------------------------------------------------------------------
 106 //Signal        Used As         USE         I/O     LVL
 107 //---------------------------------------------------------------------------------
 108 //
 109 // GPIO0    FP_AUDIO_DETECT     G       I
 110 // GPIO1    SMC_RUNTIME_SCI#    G       I
 111 // GPIO2        INT_PIRQE_N     N       I
 112 // GPIO3    INT_PIRQF_N     N       I
 113 // GPIO4        INT_PIRQG_N     N       I
 114 // GPIO5        INT_PIRQH_N     N       I
 115 // GPIO6
 116 // GPIO7
 117 // GPIO8
 118 // GPIO9    LPC_SIO_PME     G       I
 119 // GPIO10   SMC_EXTSMI_N        G       I
 120 // GPIO11   SMBALERT- pullup    N
 121 // GPIO12   ICH_GP12        G       I
 122 // GPIO13   SMC_WAKE_SCI_N      G       I
 123 // GPIO14   LCD_PID0        G       O       H
 124 // GPIO15   CONFIG_MODE_N       G       I
 125 // GPIO16       PM_DPRSLPVR     N
 126 // GPIO17   SPI_SELECT_STRAP1
 127 //          /L_BKLTSEL0_N   G       I
 128 // GPIO18   PM_STPPCI_N     N
 129 // GPIO19
 130 // GPIO20   PM_STPCPU_N     N
 131 // GPIO21
 132 // GPIO22   REQ4B           G       I
 133 // GPIO23   L_DRQ1_N        N
 134 // GPIO24   CRB_SV_DET_N        G       O       H
 135 // GPIO25   DMI strap
 136 //          / L_BKLTSEL1_N  G       O       H
 137 // GPIO26   LCD_PID1        G       O       H
 138 // GPIO27   TPEV_DDR3L_DETECT   G       O       H
 139 // GPIO28   RF_KILL         G       O       H:enable
 140 // GPIO29   OC          N
 141 // GPIO30   OC          N
 142 // GPIO31   OC          N
 143 // GPIO32   PM_CLKRUN_N     Native
 144 // GPIO33   MFG_MODE_N      G       I
 145 // GPIO34   BOARD ID0       G       I
 146 // GPIO35
 147 // GPIO36   SV_SET_UP       G       O       H
 148 // GPIO37
 149 // GPIO38   BOARD ID1       G       I
 150 // GPIO39   BOARD ID2       G       I
 151 // GPIO48   FLASH_SEL0      N
 152 // GPIO49   H_PWRGD         N
 153
 154 #define ICH_GPI_ROUTE_SMI(Gpio)          ((( 0 << ((Gpio * 2) + 1)) | (1 << (Gpio * 2))))
 155 #define ICH_GPI_ROUTE_SCI(Gpio)          ((( 1 << ((Gpio * 2) + 1)) | (0 << (Gpio * 2))))
 156
 157 #define   GPIO_USE_SEL_VAL              0X1F42F7C3
 158 #define   GPIO_USE_SEL2_VAL             0X000000D6
 159 #define   GPIO_IO_SEL_VAL               0X1042B73F
 160 #define   GPIO_IO_SEL2_VAL              0X000100C6
 161 #define   GPIO_LVL_VAL                  0X1F15F601
 162 #define   GPIO_LVL2_VAL                 0X000200D7
 163 #define   GPIO_INV_VAL                  0x00002602
 164 #define   GPIO_BLNK_VAL                 0x00040000
 165 #define   ICH_GPI_ROUTE (ICH_GPI_ROUTE_SCI(13) | ICH_GPI_ROUTE_SCI(1))
 166
 167 #endif