Vlv2TbltDevicePkg/Library/CpuIA32Lib/X64/Cpu.asm

   1
   2 TITLE   Cpu.asm: Assembly code for the x64 resources
   3
   4 ;
   5 ; This file contains an 'Intel Sample Driver' and is
   6 ; licensed for Intel CPUs and chipsets under the terms of your
   7 ; license agreement with Intel or your vendor.  This file may
   8 ; be modified by the user, subject to additional terms of the
   9 ; license agreement
  10 ;
  11 ;
  12 ; Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
  13 ;
  14 ; This program and the accompanying materials are licensed and made available under
  15 ; the terms and conditions of the BSD License that accompanies this distribution.
  16 ; The full text of the license may be found at
  17 ; http://opensource.org/licenses/bsd-license.php.
  18 ;
  19 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  20 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  21 ;
  22 ;
  23 ;
  24 ;
  25 ;
  26 ;*   Module Name:
  27 ;*
  28 ;*    Cpu.asm
  29 ;*
  30 ;*   Abstract:
  31 ;*
  32 ;------------------------------------------------------------------------------
  33
  34 text    SEGMENT
  35
  36
  37 ;------------------------------------------------------------------------------
  38 ;  VOID
  39 ;  EfiHalt (
  40 ;    VOID
  41 ;    )
  42 ;------------------------------------------------------------------------------
  43 EfiHalt PROC    PUBLIC
  44     hlt
  45     ret
  46 EfiHalt ENDP
  47
  48
  49 ;------------------------------------------------------------------------------
  50 ;  VOID
  51 ;  EfiWbinvd (
  52 ;    VOID
  53 ;    )
  54 ;------------------------------------------------------------------------------
  55 EfiWbinvd PROC    PUBLIC
  56     wbinvd
  57     ret
  58 EfiWbinvd ENDP
  59
  60
  61 ;------------------------------------------------------------------------------
  62 ;  VOID
  63 ;  EfiInvd (
  64 ;    VOID
  65 ;    )
  66 ;------------------------------------------------------------------------------
  67 EfiInvd PROC    PUBLIC
  68     invd
  69     ret
  70 EfiInvd ENDP
  71
  72 ;------------------------------------------------------------------------------
  73 ;  VOID
  74 ;  EfiCpuid (
  75 ;    IN   UINT32              RegisterInEax,          // rcx
  76 ;    OUT  EFI_CPUID_REGISTER  *Reg           OPTIONAL // rdx
  77 ;    )
  78 ;------------------------------------------------------------------------------
  79 EfiCpuid PROC   PUBLIC
  80     push  rbx
  81
  82     mov   r8,   rdx         ; r8 = *Reg
  83     mov   rax,  rcx         ; RegisterInEax
  84     cpuid
  85     cmp   r8,   0
  86     je    _Exit
  87     mov   [r8 +  0], eax    ; Reg->RegEax
  88     mov   [r8 +  4], ebx    ; Reg->RegEbx
  89     mov   [r8 +  8], ecx    ; Reg->RegEcx
  90     mov   [r8 + 12], edx    ; Reg->RegEdx
  91
  92 _Exit:
  93     pop   rbx
  94     ret
  95 EfiCpuid  ENDP
  96
  97 ;------------------------------------------------------------------------------
  98 ;  UINT64
  99 ;  EfiReadMsr (
 100 ;    IN   UINT32  Index,  // rcx
 101 ;    )
 102 ;------------------------------------------------------------------------------
 103 EfiReadMsr PROC  PUBLIC
 104     rdmsr
 105     sal     rdx, 32   ; edx:eax -> rax
 106     or      rax, rdx  ; rax = edx:eax
 107     ret
 108 EfiReadMsr  ENDP
 109
 110 ;------------------------------------------------------------------------------
 111 ;  VOID
 112 ;  EfiWriteMsr (
 113 ;    IN   UINT32  Index,  // rcx
 114 ;    IN   UINT64  Value   // rdx
 115 ;    )
 116 ;------------------------------------------------------------------------------
 117 EfiWriteMsr PROC   PUBLIC
 118     mov     rax,  rdx   ; rdx = Value
 119     sar     rdx,  32    ; convert rdx to edx upper 32-bits
 120     wrmsr               ; wrmsr[ecx] result = edx:eax
 121     ret
 122 EfiWriteMsr  ENDP
 123
 124
 125 ;------------------------------------------------------------------------------
 126 ; UINT64
 127 ; EfiReadTsc (
 128 ;   VOID
 129 ;   );
 130 ;------------------------------------------------------------------------------
 131 EfiReadTsc PROC    PUBLIC
 132     rdtsc
 133     shl     rax, 32
 134     shrd    rax, rdx, 32
 135     ret
 136 EfiReadTsc  ENDP
 137
 138 ;------------------------------------------------------------------------------
 139 ; VOID
 140 ; EfiDisableCache (
 141 ;   VOID
 142 ;   );
 143 ;------------------------------------------------------------------------------
 144 EfiDisableCache PROC    PUBLIC
 145 ; added a check to see if cache is already disabled. If it is, then skip.
 146     mov   rax, cr0
 147     and   rax, 060000000h
 148     cmp   rax, 0
 149     jne   @f
 150     mov   rax, cr0
 151     or    rax, 060000000h
 152     mov   cr0, rax
 153     wbinvd
 154 @@:
 155     ret
 156 EfiDisableCache ENDP
 157
 158 ;------------------------------------------------------------------------------
 159 ; VOID
 160 ; EfiEnableCache (
 161 ;   VOID
 162 ;   );
 163 ;------------------------------------------------------------------------------
 164 EfiEnableCache PROC    PUBLIC
 165     wbinvd
 166     mov   rax, cr0
 167     and   rax, 09fffffffh
 168     mov   cr0, rax
 169     ret
 170 EfiEnableCache ENDP
 171
 172 ;------------------------------------------------------------------------------
 173 ; UINTN
 174 ; EfiGetEflags (
 175 ;   VOID
 176 ;   );
 177 ;------------------------------------------------------------------------------
 178 EfiGetEflags PROC    PUBLIC
 179     pushfq
 180     pop   rax
 181     ret
 182 EfiGetEflags  ENDP
 183
 184 ;------------------------------------------------------------------------------
 185 ; VOID
 186 ; EfiDisableInterrupts (
 187 ;   VOID
 188 ;   );
 189 ;------------------------------------------------------------------------------
 190 EfiDisableInterrupts PROC    PUBLIC
 191     cli
 192     ret
 193 EfiDisableInterrupts  ENDP
 194
 195 ;------------------------------------------------------------------------------
 196 ; VOID
 197 ; EfiEnableInterrupts (
 198 ;   VOID
 199 ;   );
 200 ;------------------------------------------------------------------------------
 201 EfiEnableInterrupts PROC    PUBLIC
 202     sti
 203     ret
 204 EfiEnableInterrupts  ENDP
 205 ;------------------------------------------------------------------------------
 206 ;  VOID
 207 ;  EfiCpuidExt (
 208 ;    IN   UINT32              RegisterInEax,
 209 ;    IN   UINT32              CacheLevel,
 210 ;    OUT  EFI_CPUID_REGISTER  *Regs
 211 ;    )
 212 ;------------------------------------------------------------------------------
 213 EfiCpuidExt PROC    PUBLIC
 214      push   rbx
 215      mov    rax, rcx          ; rax = RegisterInEax
 216      mov    rcx, rdx          ; rcx = CacheLevel
 217
 218      cpuid
 219      mov    [r8 + 0 ],  eax   ; Reg->RegEax
 220      mov    [r8 + 4 ],  ebx   ; Reg->RegEbx
 221      mov    [r8 + 8 ],  ecx   ; Reg->RegEcx
 222      mov    [r8 + 12],  edx   ; Reg->RegEdx
 223
 224      pop rbx
 225      ret
 226 EfiCpuidExt  ENDP
 227 END