Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.c

   1 /** @file
   2
   3   Copyright (c) 2004  - 2014, Intel Corporation. All rights reserved.<BR>
   4
   5   This program and the accompanying materials are licensed and made available under
   6   the terms and conditions of the BSD License that accompanies this distribution.
   7   The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php.
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13
  14 Module Name:
  15
  16     SioInit.c
  17
  18 Abstract:
  19
  20     Functions for LpcSio initialization
  21
  22 --*/
  23
  24 #include "PlatformSerialPortLib.h"
  25 #include "SioInit.h"
  26
  27 typedef struct {
  28   UINT8 Register;
  29   UINT8 Value;
  30 } EFI_SIO_TABLE;
  31
  32 EFI_SIO_TABLE mSioTableWpcn381u[] = {
  33     {0x29, 0x0A0},
  34     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device
  35     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB
  36     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
  37     {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4
  38     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  39     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device
  40     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB
  41     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
  42     {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3
  43     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  44     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device
  45     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB
  46     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB
  47     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  48     {0x21, 0x001},                                                                        // Global Device Enable
  49     {0x26, 0x000}
  50 };
  51
  52 EFI_SIO_TABLE mSioTableWdcp376[] = {
  53     {0x29, 0x0A0},
  54     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART0},                                       // Select UART0 device
  55     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS >> 8)},       // Set Base Address MSB
  56     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT0_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
  57     {WPCN381U_IRQ1_REGISTER, 0x014},                                                      // Set to IRQ4
  58     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  59     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_UART1},                                       // Select UART1 device
  60     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS >> 8)},       // Set Base Address MSB
  61     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_SERIAL_PORT1_BASE_ADDRESS & 0x00FF)},   // Set Base Address LSB
  62     {WPCN381U_IRQ1_REGISTER, 0x013},                                                      // Set to IRQ3
  63     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  64     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_GPIO},                                        // Select GPIO device
  65     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS >> 8)},               // Set Base Address MSB
  66     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_GPIO_BASE_ADDRESS & 0x00FF)},           // Set Base Address LSB
  67     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  68     {0x21, 0x001},                                                                        // Global Device Enable
  69     {0x26, 0x000},
  70     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2K},                                        // Select PS2 Keyboard
  71     {WPCN381U_BASE1_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS >> 8)},                // Set Base Address MSB
  72     {WPCN381U_BASE1_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE1_ADDRESS & 0x00FF)},            // Set Base Address LSB
  73     {WPCN381U_BASE2_HI_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS >> 8)},                // Set Base Address MSB
  74     {WPCN381U_BASE2_LO_REGISTER, (UINT8)(WPCN381U_KB_BASE2_ADDRESS & 0x00FF)},            // Set Base Address LSB
  75     {WPCN381U_IRQ1_REGISTER, 0x011},                                                      // Set to IRQ1
  76     {0xF0, (SIO_KBC_CLOCK << 6)},                                                         // Select KBC Clock Source
  77     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE},                                // Enable it with Activation bit
  78     {WPCN381U_LD_SEL_REGISTER, WPCN381U_LDN_PS2M},                                        // Select PS2 Mouse
  79     {WPCN381U_IRQ1_REGISTER, 0x01c},                                                      // Set to IRQ12
  80     {WPCN381U_ACTIVATE_REGISTER, WPCN381U_ACTIVATE_VALUE}                                 // Enable it with Activation bit
  81 };
  82
  83 /**
  84   Initialization for SIO.
  85
  86   @param FfsHeader     FV this PEIM was loaded from.
  87   @param PeiServices   General purpose services available to every PEIM.
  88
  89   None
  90
  91 **/
  92 VOID
  93 InitializeSio (
  94   VOID
  95   )
  96 {
  97   UINT16          Index;
  98   UINT16          IndexPort;
  99   UINT16          DataPort;
 100
 101   //
 102   // Super I/O initialization for Winbond WPCN381U
 103   //
 104   IndexPort  = WPCN381U_CONFIG_INDEX;
 105   DataPort   = WPCN381U_CONFIG_DATA;
 106
 107   //
 108   // Check for Winbond WPCN381U
 109   //
 110   IoWrite8 (IndexPort, WPCN381U_DEV_ID_REGISTER);   // Winbond WPCN381U Device ID register is 0x20
 111
 112   if (IoRead8 (DataPort) == WPCN381U_CHIP_ID) {   // Winbond WPCN381U Device ID is 0xF4
 113     //
 114     // Configure WPCN381U SIO
 115     //
 116     for (Index = 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI_SIO_TABLE); Index++) {
 117       IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);
 118       IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);
 119     }
 120   }
 121
 122   if (IoRead8 (DataPort) == WDCP376_CHIP_ID) {   // Winbond WDCP376 Device ID is 0xF1
 123     //
 124     // Configure WDCP376 SIO
 125     //
 126     for (Index = 0; Index < sizeof (mSioTableWdcp376) / sizeof (EFI_SIO_TABLE); Index++) {
 127       IoWrite8 (IndexPort, mSioTableWdcp376[Index].Register);
 128       IoWrite8 (DataPort, mSioTableWdcp376[Index].Value);
 129     }
 130   }
 131   return;
 132 }