Vlv2TbltDevicePkg/Library/SerialPortLib/SioInit.h

   1 /** @file
   2   Header file of Serial port hardware definition.
   3
   4   Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved.<BR>
   5
   6   This program and the accompanying materials are licensed and made available under
   7   the terms and conditions of the BSD License that accompanies this distribution.
   8   The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14   This software and associated documentation
  15   (if any) is furnished under a license and may only be used or
  16   copied in accordance with the terms of the license.  Except as
  17   permitted by such license, no part of this software or
  18   documentation may be reproduced, stored in a retrieval system, or
  19   transmitted in any form or by any means without the express written
  20   consent of Intel Corporation.
  21
  22   Module Name:  PlatformSerialPortLib.h
  23
  24 **/
  25
  26 #ifndef _SIO_INIT_H_
  27 #define _SIO_INIT_H_
  28
  29 #define WPCN381U_CONFIG_INDEX               0x2E
  30 #define WPCN381U_CONFIG_DATA                0x2F
  31 #define WPCN381U_CONFIG_INDEX1              0x164E
  32 #define WPCN381U_CONFIG_DATA1               0x164F
  33 #define WPCN381U_CHIP_ID                    0xF4
  34 #define WDCP376_CHIP_ID                     0xF1
  35
  36 //
  37 // SIO Logical Devices Numbers
  38 //
  39 #define WPCN381U_LDN_UART0                  0x03   // LDN for Serial Port Controller
  40 #define WPCN381U_LDN_UART1                  0x02   // LDN for Parallel Port Controller
  41 #define WPCN381U_LDN_PS2K                   0x06   // LDN for PS2 Keyboard Controller
  42 #define WPCN381U_LDN_PS2M                   0x05   // LDN for PS2 Mouse Controller
  43 #define WPCN381U_KB_BASE1_ADDRESS           0x60   // Base Address of KB controller
  44 #define WPCN381U_KB_BASE2_ADDRESS           0x64   // Base Address of KB controller
  45 #define SIO_KBC_CLOCK                       0x01   // 0/1/2 - 8/12/16 MHz KBC Clock Source
  46 #define WPCN381U_LDN_GPIO                   0x07   // LDN for GPIO
  47
  48 //
  49 // SIO Registers Layout
  50 //
  51 #define WPCN381U_LD_SEL_REGISTER            0x07   // Logical Device Select Register Address
  52 #define WPCN381U_DEV_ID_REGISTER            0x20   // Device Identification Register Address
  53 #define WPCN381U_ACTIVATE_REGISTER          0x30   // Device Identification Register Address
  54 #define WPCN381U_BASE1_HI_REGISTER          0x60   // Device BaseAddres Register #1 MSB Address
  55 #define WPCN381U_BASE1_LO_REGISTER          0x61   // Device BaseAddres Register #1 LSB Address
  56 #define WPCN381U_BASE2_HI_REGISTER          0x62   // Device BaseAddres Register #1 MSB Address
  57 #define WPCN381U_BASE2_LO_REGISTER          0x63   // Device Ba1eAddres Register #1 LSB Address
  58 #define WPCN381U_IRQ1_REGISTER              0x70   // Device IRQ Register #1 Address
  59 #define WPCN381U_IRQ2_REGISTER              0x71   // Device IRQ Register #2 Address
  60
  61 //
  62 // SIO Activation Values
  63 //
  64 #define WPCN381U_ACTIVATE_VALUE             0x01   // Value to activate Device
  65 #define WPCN381U_DEACTIVATE_VALUE           0x00   // Value to deactivate Device
  66
  67 //
  68 // SIO GPIO
  69 //
  70 #define WPCN381U_GPIO_BASE_ADDRESS          0x0A20 // SIO GPIO Base Address
  71
  72 //
  73 // SIO Serial Port Settings
  74 //
  75 #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS  0x03F8 // Base Address of Serial Port 0 (COMA / UART0)
  76 #define WPCN381U_SERIAL_PORT1_BASE_ADDRESS  0x02F8 // Base Address of Serial Port 1 (COMB / UART1)
  77
  78 #endif