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[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / Platform.c
1 /** @file
2
3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
4
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13
14 Module Name:
15
16
17 Platform.c
18
19 Abstract:
20
21 Platform Initialization Driver.
22
23
24 --*/
25
26 #include "PlatformDxe.h"
27 #include "Platform.h"
28 #include "PchCommonDefinitions.h"
29 #include <Protocol/UsbPolicy.h>
30 #include <Protocol/PchPlatformPolicy.h>
31 #include <Protocol/TpmMp.h>
32 #include <Protocol/CpuIo2.h>
33 #include <Library/S3BootScriptLib.h>
34 #include <Guid/PciLanInfo.h>
35 #include <Guid/ItkData.h>
36 #include <Library/PciLib.h>
37 #include <PlatformBootMode.h>
38 #include <Guid/EventGroup.h>
39 #include <Guid/Vlv2Variable.h>
40 #include <Protocol/GlobalNvsArea.h>
41 #include <Protocol/IgdOpRegion.h>
42 #include <Library/PcdLib.h>
43
44 //
45 // VLV2 GPIO GROUP OFFSET
46 //
47 #define GPIO_SCORE_OFFSET 0x0000
48 #define GPIO_NCORE_OFFSET 0x1000
49 #define GPIO_SSUS_OFFSET 0x2000
50
51 typedef struct {
52 UINT32 offset;
53 UINT32 val;
54 } CFIO_PNP_INIT;
55
56 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
57 {
58 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
59 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
60 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
61 };
62
63
64 EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
65 EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
66 SYSTEM_CONFIGURATION mSystemConfiguration;
67 SYSTEM_PASSWORDS mSystemPassword;
68 EFI_HANDLE mImageHandle;
69 BOOLEAN mMfgMode = FALSE;
70 VOID *mDxePlatformStringPack;
71 UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
72 extern CHAR16 gItkDataVarName[];
73
74
75 EFI_PLATFORM_INFO_HOB mPlatformInfo;
76 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
77 EFI_EVENT mReadyToBootEvent;
78
79 UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
80 UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
81 UINT32 mSubsystemVidDid;
82 UINT32 mSubsystemAudioVidDid;
83
84 UINTN mPciLanCount = 0;
85 VOID *mPciLanInfo = NULL;
86 UINTN SpiBase;
87
88 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
89 ProgramToneFrequency,
90 GenerateBeepTone
91 };
92
93 EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
94
95
96 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
97 {
98 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
99 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
100 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
101 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
102 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
103 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
104 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
105 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
106 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
107 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
108 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
109 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
110 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
111 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
112 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
113 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
114 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
115 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
116 };
117
118 VOID
119 EfiOrMem (
120 IN VOID *Destination,
121 IN VOID *Source,
122 IN UINTN Length
123 );
124
125 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
126 STATIC
127 VOID
128 InitFirmwareId();
129 #endif
130
131
132 VOID
133 InitializeClockRouting(
134 );
135
136 VOID
137 InitializeSlotInfo (
138 );
139
140 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
141 VOID
142 InitializeSensorInfoVariable (
143 );
144 #endif
145
146 VOID
147 InitTcoReset (
148 );
149
150 VOID
151 InitExI ();
152
153 VOID
154 InitItk();
155
156 VOID
157 InitPlatformBootMode();
158
159 VOID
160 InitMfgAndConfigModeStateVar();
161
162 VOID
163 InitPchPlatformPolicy (
164 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
165 );
166
167 VOID
168 InitVlvPlatformPolicy (
169 );
170
171 VOID
172 InitSioPlatformPolicy(
173 );
174
175 VOID
176 PchInitBeforeBoot(
177 );
178
179 VOID
180 UpdateDVMTSetup(
181 );
182
183 VOID
184 InitPlatformUsbPolicy (
185 VOID
186 );
187
188 VOID
189 InitRC6Policy(
190 VOID
191 );
192
193
194 VOID
195 TristateLpcGpioConfig (
196 IN UINT32 Gpio_Mmio_Offset,
197 IN UINT32 Gpio_Pin_Num,
198 GPIO_CONF_PAD_INIT* Gpio_Conf_Data
199 )
200
201 {
202 UINT32 index;
203 UINT32 mmio_conf0;
204 UINT32 mmio_padval;
205 PAD_CONF0 conf0_val;
206 PAD_VAL pad_val;
207
208 //
209 // GPIO WELL -- Memory base registers
210 //
211
212 //
213 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
214 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
215 //
216
217 for(index=0; index < Gpio_Pin_Num; index++)
218 {
219 //
220 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
221 //
222 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
223 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
224
225 #ifdef EFI_DEBUG
226 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
227
228 #endif
229 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
230 Gpio_Conf_Data[index].usage,
231 Gpio_Conf_Data[index].func,
232 Gpio_Conf_Data[index].int_type,
233 Gpio_Conf_Data[index].pull,
234 mmio_conf0));
235
236 //
237 // Step 1: PadVal Programming
238 //
239 pad_val.dw = MmioRead32(mmio_padval);
240
241 //
242 // Config PAD_VAL only for GPIO (Non-Native) Pin
243 //
244 if(Native != Gpio_Conf_Data[index].usage)
245 {
246 pad_val.dw &= ~0x6; // Clear bits 1:2
247 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
248
249 //
250 // set GPO default value
251 //
252 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
253 {
254 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
255 }
256 }
257
258
259 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
260
261 MmioWrite32(mmio_padval, pad_val.dw);
262
263 //
264 // Step 2: CONF0 Programming
265 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
266 //
267 conf0_val.dw = MmioRead32(mmio_conf0);
268
269 //
270 // Set Function #
271 //
272 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
273
274 if(GPO == Gpio_Conf_Data[index].usage)
275 {
276 //
277 // If used as GPO, then internal pull need to be disabled
278 //
279 conf0_val.r.Pull_assign = 0; // Non-pull
280 }
281 else
282 {
283 //
284 // Set PullUp / PullDown
285 //
286 if(P_20K_H == Gpio_Conf_Data[index].pull)
287 {
288 conf0_val.r.Pull_assign = 0x1; // PullUp
289 conf0_val.r.Pull_strength = 0x2;// 20K
290 }
291 else if(P_20K_L == Gpio_Conf_Data[index].pull)
292 {
293 conf0_val.r.Pull_assign = 0x2; // PullDown
294 conf0_val.r.Pull_strength = 0x2;// 20K
295 }
296 else if(P_NONE == Gpio_Conf_Data[index].pull)
297 {
298 conf0_val.r.Pull_assign = 0; // Non-pull
299 }
300 else
301 {
302 ASSERT(FALSE); // Invalid value
303 }
304 }
305
306 //
307 // Set INT Trigger Type
308 //
309 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
310
311 //
312 // Set INT Trigger Type
313 //
314 if(TRIG_ == Gpio_Conf_Data[index].int_type)
315 {
316 //
317 // Interrupt not capable, clear bits 27:24
318 //
319 }
320 else
321 {
322 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
323 }
324
325 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
326
327 //
328 // Write back the targeted GPIO config value according to platform (board) GPIO setting
329 //
330 MmioWrite32 (mmio_conf0, conf0_val.dw);
331 }
332
333 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
334 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
335 //
336 }
337
338 VOID
339 EFIAPI
340 SpiBiosProtectionFunction(
341 EFI_EVENT Event,
342 VOID *Context
343 )
344 {
345
346 UINTN mPciD31F0RegBase;
347 UINTN BiosFlaLower = 0;
348 UINTN BiosFlaLimit = 0x7fffff;
349
350 BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
351
352
353 mPciD31F0RegBase = MmPciAddress (0,
354 DEFAULT_PCI_BUS_NUMBER_PCH,
355 PCI_DEVICE_NUMBER_PCH_LPC,
356 PCI_FUNCTION_NUMBER_PCH_LPC,
357 0
358 );
359 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
360
361 //
362 //Set SMM_BWP, WPD and LE bit
363 //
364 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
365 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
366 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
367
368 //
369 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
370 //
371 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
372 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
373 //
374 //Already locked. we could take no action here
375 //
376 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
377 return;
378 }
379
380 //
381 //Set PR0
382 //
383 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
384 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
385 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));
386
387 //
388 //Lock down PR0
389 //
390 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
391
392 //
393 // Verify if it's really locked.
394 //
395 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
396 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
397 }
398
399 return;
400
401 }
402
403 VOID
404 EFIAPI
405 InitPciDevPME (
406 EFI_EVENT Event,
407 VOID *Context
408 )
409 {
410 UINTN VarSize;
411 EFI_STATUS Status;
412
413 VarSize = sizeof(SYSTEM_CONFIGURATION);
414 Status = gRT->GetVariable(
415 NORMAL_SETUP_NAME,
416 &gEfiNormalSetupGuid,
417 NULL,
418 &VarSize,
419 &mSystemConfiguration
420 );
421
422 //
423 //Program HDA PME_EN
424 //
425 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
426
427 //
428 //Program SATA PME_EN
429 //
430 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
431
432 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
433 if (mSystemConfiguration.EhciPllCfgEnable != 1) {
434 //
435 //Program EHCI PME_EN
436 //
437 PchMmPci32Or (
438 0,
439 0,
440 PCI_DEVICE_NUMBER_PCH_USB,
441 PCI_FUNCTION_NUMBER_PCH_EHCI,
442 R_PCH_EHCI_PWR_CNTL_STS,
443 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
444 );
445 }
446 {
447 UINTN EhciPciMmBase;
448 UINT32 Buffer32 = 0;
449
450 EhciPciMmBase = MmPciAddress (0,
451 0,
452 PCI_DEVICE_NUMBER_PCH_USB,
453 PCI_FUNCTION_NUMBER_PCH_EHCI,
454 0
455 );
456 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
457 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
458 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
459 }
460 }
461
462 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
463
464 #endif
465
466
467 EFI_STATUS
468 EFIAPI
469 TristateLpcGpioS0i3Config (
470 UINT32 Gpio_Mmio_Offset,
471 UINT32 Gpio_Pin_Num,
472 CFIO_PNP_INIT* Gpio_Conf_Data
473 )
474 {
475
476 UINT32 index;
477 UINT32 mmio_reg;
478 UINT32 mmio_val;
479
480 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
481
482 for(index=0; index < Gpio_Pin_Num; index++)
483 {
484 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
485
486 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
487 mmio_val = 0;
488 mmio_val = MmioRead32(mmio_reg);
489
490 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
491 }
492
493 return EFI_SUCCESS;
494 }
495
496
497 EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
498
499 /**
500 Event Notification during exit boot service to enabel ACPI mode
501
502 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
503
504 Clear all ACPI event status and disable all ACPI events
505 Disable PM sources except power button
506 Clear status bits
507
508 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
509
510 Update EC to disable SMI and enable SCI
511
512 Enable SCI
513
514 Enable PME_B0_EN in GPE0a_EN
515
516 @param Event - EFI Event Handle
517 @param Context - Pointer to Notify Context
518
519 @retval Nothing
520
521 **/
522 VOID
523 EFIAPI
524 EnableAcpiCallback (
525 IN EFI_EVENT Event,
526 IN VOID *Context
527 )
528 {
529 UINT32 RegData32;
530 UINT16 Pm1Cnt;
531 UINT16 AcpiBase;
532 UINT32 Gpe0aEn;
533
534 AcpiBase = MmioRead16 (
535 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
536 PCI_DEVICE_NUMBER_PCH_LPC,
537 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
538 ) & B_PCH_LPC_ACPI_BASE_BAR;
539
540 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
541
542 //
543 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
544 //
545 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
546 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
547 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
548
549 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
550 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
551 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
552
553 //
554 // Disable PM sources except power button
555 // power button is enabled only for PCAT. Disabled it on Tablet platform
556 //
557
558 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
559 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
560
561 //
562 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
563 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
564 //
565 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
566 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
567
568 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
569 RegData32 &= ~(BIT7);
570 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
571
572 //
573 // Enable SCI
574 //
575 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
576 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
577 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
578
579 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
580
581 //
582 // Enable PME_B0_EN in GPE0a_EN
583 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
584 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
585 //
586 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
587 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
588 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
589
590 }
591
592 /**
593
594 Routine Description:
595
596 This is the standard EFI driver point for the Driver. This
597 driver is responsible for setting up any platform specific policy or
598 initialization information.
599
600 @param ImageHandle Handle for the image of this driver.
601 @param SystemTable Pointer to the EFI System Table.
602
603 @retval EFI_SUCCESS Policy decisions set.
604
605 **/
606 EFI_STATUS
607 EFIAPI
608 InitializePlatform (
609 IN EFI_HANDLE ImageHandle,
610 IN EFI_SYSTEM_TABLE *SystemTable
611 )
612 {
613 EFI_STATUS Status;
614 UINTN VarSize;
615 EFI_HANDLE Handle = NULL;
616
617 EFI_EVENT mEfiExitBootServicesEvent;
618
619 //
620 mImageHandle = ImageHandle;
621
622 Status = gBS->InstallProtocolInterface (
623 &Handle,
624 &gEfiSpeakerInterfaceProtocolGuid,
625 EFI_NATIVE_INTERFACE,
626 &mSpeakerInterface
627 );
628
629 Status = gBS->LocateProtocol (
630 &gEfiPciRootBridgeIoProtocolGuid,
631 NULL,
632 (VOID **) &mPciRootBridgeIo
633 );
634 ASSERT_EFI_ERROR (Status);
635
636 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
637 Status = gRT->GetVariable(
638 L"PlatformInfo",
639 &gEfiVlv2VariableGuid,
640 NULL,
641 &VarSize,
642 &mPlatformInfo
643 );
644
645 //
646 // Initialize Product Board ID variable
647 //
648 InitMfgAndConfigModeStateVar();
649 InitPlatformBootMode();
650
651 //
652 // Install Observable protocol
653 //
654 InitializeObservableProtocol();
655
656
657 VarSize = sizeof(SYSTEM_CONFIGURATION);
658 Status = gRT->GetVariable(
659 NORMAL_SETUP_NAME,
660 &gEfiNormalSetupGuid,
661 NULL,
662 &VarSize,
663 &mSystemConfiguration
664 );
665
666
667 Status = EfiCreateEventReadyToBootEx (
668 TPL_CALLBACK,
669 ReadyToBootFunction,
670 NULL,
671 &mReadyToBootEvent
672 );
673
674 //
675 // Create a ReadyToBoot Event to run the PME init process
676 //
677 Status = EfiCreateEventReadyToBootEx (
678 TPL_CALLBACK,
679 InitPciDevPME,
680 NULL,
681 &mReadyToBootEvent
682 );
683 //
684 // Create a ReadyToBoot Event to run enable PR0 and lock down
685 //
686 if(mSystemConfiguration.SpiRwProtect==1) {
687 Status = EfiCreateEventReadyToBootEx (
688 TPL_CALLBACK,
689 SpiBiosProtectionFunction,
690 NULL,
691 &mReadyToBootEvent
692 );
693 }
694
695 ReportStatusCodeEx (
696 EFI_PROGRESS_CODE,
697 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
698 0,
699 &gEfiCallerIdGuid,
700 NULL,
701 NULL,
702 0
703 );
704
705 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
706 //
707 // Initialize Sensor Info variable
708 //
709 InitializeSensorInfoVariable();
710 #endif
711 InitPchPlatformPolicy(&mPlatformInfo);
712 InitVlvPlatformPolicy();
713
714 //
715 // Add usb policy
716 //
717 InitPlatformUsbPolicy();
718 InitSioPlatformPolicy();
719 InitializeClockRouting();
720 InitializeSlotInfo();
721 InitTcoReset();
722
723 //
724 //Init ExI
725 //
726 InitExI();
727
728 ReportStatusCodeEx (
729 EFI_PROGRESS_CODE,
730 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
731 0,
732 &gEfiCallerIdGuid,
733 NULL,
734 NULL,
735 0
736 );
737
738 //
739 // Install PCI Bus Driver Hook
740 //
741 PciBusDriverHook();
742
743 InitItk();
744
745 ReportStatusCodeEx (
746 EFI_PROGRESS_CODE,
747 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
748 0,
749 &gEfiCallerIdGuid,
750 NULL,
751 NULL,
752 0
753 );
754
755
756 //
757 // Initialize Password States and Callbacks
758 //
759 PchInitBeforeBoot();
760
761 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
762
763 #endif
764
765 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
766 //
767 // Re-write Firmware ID if it is changed
768 //
769 InitFirmwareId();
770 #endif
771
772 ReportStatusCodeEx (
773 EFI_PROGRESS_CODE,
774 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
775 0,
776 &gEfiCallerIdGuid,
777 NULL,
778 NULL,
779 0
780 );
781
782
783 Status = gBS->CreateEventEx (
784 EVT_NOTIFY_SIGNAL,
785 TPL_NOTIFY,
786 EnableAcpiCallback,
787 NULL,
788 &gEfiEventExitBootServicesGuid,
789 &mEfiExitBootServicesEvent
790 );
791
792
793 //
794 // Tristae Lpc pins at last moment
795 //
796 if (mSystemConfiguration.TristateLpc == 1)
797 {
798 }
799
800 return EFI_SUCCESS;
801 }
802
803 /**
804 Source Or Destination with Length bytes.
805
806 @param[in] Destination Target memory
807 @param[in] Source Source memory
808 @param[in] Length Number of bytes
809
810 @retval None
811
812 **/
813 VOID
814 EfiOrMem (
815 IN VOID *Destination,
816 IN VOID *Source,
817 IN UINTN Length
818 )
819 {
820 CHAR8 *Destination8;
821 CHAR8 *Source8;
822
823 if (Source < Destination) {
824 Destination8 = (CHAR8 *) Destination + Length - 1;
825 Source8 = (CHAR8 *) Source + Length - 1;
826 while (Length--) {
827 *(Destination8--) |= *(Source8--);
828 }
829 } else {
830 Destination8 = (CHAR8 *) Destination;
831 Source8 = (CHAR8 *) Source;
832 while (Length--) {
833 *(Destination8++) |= *(Source8++);
834 }
835 }
836 }
837
838 VOID
839 PchInitBeforeBoot()
840 {
841 //
842 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
843 //
844 S3BootScriptSaveMemWrite (
845 EfiBootScriptWidthUint32,
846 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
847 1,
848 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
849
850 S3BootScriptSaveMemWrite (
851 EfiBootScriptWidthUint32,
852 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
853 1,
854 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
855
856 S3BootScriptSaveMemWrite (
857 EfiBootScriptWidthUint16,
858 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
859 1,
860 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
861
862 S3BootScriptSaveMemWrite (
863 EfiBootScriptWidthUint16,
864 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
865 1,
866 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
867
868 //
869 // Saved MTPMC_1 for S3 resume.
870 //
871 S3BootScriptSaveMemWrite (
872 EfiBootScriptWidthUint32,
873 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
874 1,
875 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
876 return;
877 }
878
879 VOID
880 EFIAPI
881 ReadyToBootFunction (
882 EFI_EVENT Event,
883 VOID *Context
884 )
885 {
886 EFI_STATUS Status;
887 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
888 EFI_ISA_ACPI_DEVICE_ID IsaDevice;
889 UINTN Size;
890 UINT16 State;
891 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
892 EFI_CPU_IO_PROTOCOL *CpuIo;
893 UINT8 Data;
894 UINT8 ReceiveBuffer [64];
895 UINT32 ReceiveBufferSize;
896
897 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
898 0x00, 0x00, 0x00, 0x0A,
899 0x00, 0x00, 0x00, 0x5D};
900 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
901 0x00, 0x00, 0x00, 0x0C,
902 0x40, 0x00, 0x00, 0x0A,
903 0x00, 0x00};
904 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
905 0x00, 0x00, 0x00, 0x0A,
906 0x00, 0x00, 0x00, 0x70};
907 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
908 0x00, 0x00, 0x00, 0x0A,
909 0x00, 0x00, 0x00, 0x6F};
910 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
911 0x00, 0x00, 0x00, 0x0B,
912 0x00, 0x00, 0x00, 0x72,
913 0x00};
914 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
915 0x00, 0x00, 0x00, 0x0B,
916 0x00, 0x00, 0x00, 0x71,
917 0x00};
918
919 Size = sizeof(UINT16);
920 Status = gRT->GetVariable (
921 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
922 &gEfiNormalSetupGuid,
923 NULL,
924 &Size,
925 &State
926 );
927
928 //
929 // Disable Floppy Controller if needed
930 //
931 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
932 if (!EFI_ERROR(Status) && (State == 0x00)) {
933 IsaDevice.HID = EISA_PNP_ID(0x604);
934 IsaDevice.UID = 0;
935 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
936 }
937
938 //
939 // save LAN info to a variable
940 //
941 if (NULL != mPciLanInfo) {
942 gRT->SetVariable (
943 L"PciLanInfo",
944 &gEfiPciLanInfoGuid,
945 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
946 mPciLanCount * sizeof(PCI_LAN_INFO),
947 mPciLanInfo
948 );
949 }
950
951 if (NULL != mPciLanInfo) {
952 gBS->FreePool (mPciLanInfo);
953 mPciLanInfo = NULL;
954 }
955
956
957 //
958 // Handle ACPI OS TPM requests here
959 //
960 Status = gBS->LocateProtocol (
961 &gEfiCpuIoProtocolGuid,
962 NULL,
963 (VOID **)&CpuIo
964 );
965 Status = gBS->LocateProtocol (
966 &gEfiTpmMpDriverProtocolGuid,
967 NULL,
968 (VOID **)&TpmMpDriver
969 );
970 if (!EFI_ERROR (Status))
971 {
972 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
973
974 //
975 // Clear pending ACPI TPM request indicator
976 //
977 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
978 if (Data != 0)
979 {
980 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
981
982 //
983 // Assert Physical Presence for these commands
984 //
985 TpmPhysicalPresenceCommand [11] = 0x20;
986 ReceiveBufferSize = sizeof(ReceiveBuffer);
987 Status = TpmMpDriver->Transmit (
988 TpmMpDriver, TpmPhysicalPresenceCommand,
989 sizeof (TpmPhysicalPresenceCommand),
990 ReceiveBuffer, &ReceiveBufferSize
991 );
992 //
993 // PF PhysicalPresence = TRUE
994 //
995 TpmPhysicalPresenceCommand [11] = 0x08;
996 ReceiveBufferSize = sizeof(ReceiveBuffer);
997 Status = TpmMpDriver->Transmit (
998 TpmMpDriver, TpmPhysicalPresenceCommand,
999 sizeof (TpmPhysicalPresenceCommand),
1000 ReceiveBuffer,
1001 &ReceiveBufferSize
1002 );
1003 if (Data == 0x01)
1004 {
1005 //
1006 // TPM_PhysicalEnable
1007 //
1008 ReceiveBufferSize = sizeof(ReceiveBuffer);
1009 Status = TpmMpDriver->Transmit (
1010 TpmMpDriver, TpmPhysicalEnableCommand,
1011 sizeof (TpmPhysicalEnableCommand),
1012 ReceiveBuffer, &ReceiveBufferSize
1013 );
1014 }
1015 if (Data == 0x02)
1016 {
1017 //
1018 // TPM_PhysicalDisable
1019 //
1020 ReceiveBufferSize = sizeof(ReceiveBuffer);
1021 Status = TpmMpDriver->Transmit (
1022 TpmMpDriver, TpmPhysicalDisableCommand,
1023 sizeof (TpmPhysicalDisableCommand),
1024 ReceiveBuffer,
1025 &ReceiveBufferSize
1026 );
1027 }
1028 if (Data == 0x03)
1029 {
1030 //
1031 // TPM_PhysicalSetDeactivated=FALSE
1032 //
1033 ReceiveBufferSize = sizeof(ReceiveBuffer);
1034 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1035 Status = TpmMpDriver->Transmit (
1036 TpmMpDriver,
1037 TpmPhysicalSetDeactivatedCommand,
1038 sizeof (TpmPhysicalSetDeactivatedCommand),
1039 ReceiveBuffer, &ReceiveBufferSize
1040 );
1041 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
1042 }
1043 if (Data == 0x04)
1044 {
1045 //
1046 // TPM_PhysicalSetDeactivated=TRUE
1047 //
1048 ReceiveBufferSize = sizeof(ReceiveBuffer);
1049 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1050 Status = TpmMpDriver->Transmit (
1051 TpmMpDriver,
1052 TpmPhysicalSetDeactivatedCommand,
1053 sizeof (TpmPhysicalSetDeactivatedCommand),
1054 ReceiveBuffer,
1055 &ReceiveBufferSize
1056 );
1057 gRT->ResetSystem (
1058 EfiResetWarm,
1059 EFI_SUCCESS,
1060 0,
1061 NULL
1062 );
1063 }
1064 if (Data == 0x05)
1065 {
1066 //
1067 // TPM_ForceClear
1068 //
1069 ReceiveBufferSize = sizeof(ReceiveBuffer);
1070 Status = TpmMpDriver->Transmit (
1071 TpmMpDriver,
1072 TpmForceClearCommand,
1073 sizeof (TpmForceClearCommand),
1074 ReceiveBuffer,
1075 &ReceiveBufferSize
1076 );
1077 gRT->ResetSystem (
1078 EfiResetWarm,
1079 EFI_SUCCESS,
1080 0,
1081 NULL
1082 );
1083 }
1084 if (Data == 0x06)
1085 {
1086 //
1087 // TPM_PhysicalEnable
1088 //
1089 ReceiveBufferSize = sizeof(ReceiveBuffer);
1090 Status = TpmMpDriver->Transmit (
1091 TpmMpDriver,
1092 TpmPhysicalEnableCommand,
1093 sizeof (TpmPhysicalEnableCommand),
1094 ReceiveBuffer,
1095 &ReceiveBufferSize
1096 );
1097 //
1098 // TPM_PhysicalSetDeactivated=FALSE
1099 //
1100 ReceiveBufferSize = sizeof(ReceiveBuffer);
1101 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1102 Status = TpmMpDriver->Transmit (
1103 TpmMpDriver,
1104 TpmPhysicalSetDeactivatedCommand,
1105 sizeof (TpmPhysicalSetDeactivatedCommand),
1106 ReceiveBuffer,
1107 &ReceiveBufferSize
1108 );
1109 gRT->ResetSystem (
1110 EfiResetWarm,
1111 EFI_SUCCESS,
1112 0,
1113 NULL
1114 );
1115 }
1116 if (Data == 0x07)
1117 {
1118 //
1119 // TPM_PhysicalSetDeactivated=TRUE
1120 //
1121 ReceiveBufferSize = sizeof(ReceiveBuffer);
1122 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1123 Status = TpmMpDriver->Transmit (
1124 TpmMpDriver,
1125 TpmPhysicalSetDeactivatedCommand,
1126 sizeof (TpmPhysicalSetDeactivatedCommand),
1127 ReceiveBuffer,
1128 &ReceiveBufferSize
1129 );
1130 //
1131 // TPM_PhysicalDisable
1132 //
1133 ReceiveBufferSize = sizeof(ReceiveBuffer);
1134 Status = TpmMpDriver->Transmit (
1135 TpmMpDriver,
1136 TpmPhysicalDisableCommand,
1137 sizeof (TpmPhysicalDisableCommand),
1138 ReceiveBuffer,
1139 &ReceiveBufferSize
1140 );
1141 gRT->ResetSystem (
1142 EfiResetWarm,
1143 EFI_SUCCESS,
1144 0,
1145 NULL
1146 );
1147 }
1148 if (Data == 0x08)
1149 {
1150 //
1151 // TPM_SetOwnerInstall=TRUE
1152 //
1153 ReceiveBufferSize = sizeof(ReceiveBuffer);
1154 TpmSetOwnerInstallCommand [10] = 0x01;
1155 Status = TpmMpDriver->Transmit (
1156 TpmMpDriver,
1157 TpmSetOwnerInstallCommand,
1158 sizeof (TpmSetOwnerInstallCommand),
1159 ReceiveBuffer,
1160 &ReceiveBufferSize
1161 );
1162 }
1163 if (Data == 0x09)
1164 {
1165 //
1166 // TPM_SetOwnerInstall=FALSE
1167 //
1168 ReceiveBufferSize = sizeof(ReceiveBuffer);
1169 TpmSetOwnerInstallCommand [10] = 0x00;
1170 Status = TpmMpDriver->Transmit (
1171 TpmMpDriver,
1172 TpmSetOwnerInstallCommand,
1173 sizeof (TpmSetOwnerInstallCommand),
1174 ReceiveBuffer,
1175 &ReceiveBufferSize
1176 );
1177 }
1178 if (Data == 0x0A)
1179 {
1180 //
1181 // TPM_PhysicalEnable
1182 //
1183 ReceiveBufferSize = sizeof(ReceiveBuffer);
1184 Status = TpmMpDriver->Transmit (
1185 TpmMpDriver,
1186 TpmPhysicalEnableCommand,
1187 sizeof (TpmPhysicalEnableCommand),
1188 ReceiveBuffer,
1189 &ReceiveBufferSize
1190 );
1191 //
1192 // TPM_PhysicalSetDeactivated=FALSE
1193 //
1194 ReceiveBufferSize = sizeof(ReceiveBuffer);
1195 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1196 Status = TpmMpDriver->Transmit (
1197 TpmMpDriver,
1198 TpmPhysicalSetDeactivatedCommand,
1199 sizeof (TpmPhysicalSetDeactivatedCommand),
1200 ReceiveBuffer,
1201 &ReceiveBufferSize
1202 );
1203 //
1204 // Do TPM_SetOwnerInstall=TRUE on next reboot
1205 //
1206
1207 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
1208
1209 gRT->ResetSystem (
1210 EfiResetWarm,
1211 EFI_SUCCESS,
1212 0,
1213 NULL
1214 );
1215 }
1216 if (Data == 0x0B)
1217 {
1218 //
1219 // TPM_SetOwnerInstall=FALSE
1220 //
1221 ReceiveBufferSize = sizeof(ReceiveBuffer);
1222 TpmSetOwnerInstallCommand [10] = 0x00;
1223 Status = TpmMpDriver->Transmit (
1224 TpmMpDriver,
1225 TpmSetOwnerInstallCommand,
1226 sizeof (TpmSetOwnerInstallCommand),
1227 ReceiveBuffer,
1228 &ReceiveBufferSize
1229 );
1230 //
1231 // TPM_PhysicalSetDeactivated=TRUE
1232 //
1233 ReceiveBufferSize = sizeof(ReceiveBuffer);
1234 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1235 Status = TpmMpDriver->Transmit (
1236 TpmMpDriver,
1237 TpmPhysicalSetDeactivatedCommand,
1238 sizeof (TpmPhysicalSetDeactivatedCommand),
1239 ReceiveBuffer,
1240 &ReceiveBufferSize
1241 );
1242 //
1243 // TPM_PhysicalDisable
1244 //
1245 ReceiveBufferSize = sizeof(ReceiveBuffer);
1246 Status = TpmMpDriver->Transmit (
1247 TpmMpDriver,
1248 TpmPhysicalDisableCommand,
1249 sizeof (TpmPhysicalDisableCommand),
1250 ReceiveBuffer,
1251 &ReceiveBufferSize
1252 );
1253 gRT->ResetSystem (
1254 EfiResetWarm,
1255 EFI_SUCCESS,
1256 0,
1257 NULL
1258 );
1259 }
1260 if (Data == 0x0E)
1261 {
1262 //
1263 // TPM_ForceClear
1264 //
1265 ReceiveBufferSize = sizeof(ReceiveBuffer);
1266 Status = TpmMpDriver->Transmit (
1267 TpmMpDriver,
1268 TpmForceClearCommand,
1269 sizeof (TpmForceClearCommand),
1270 ReceiveBuffer,
1271 &ReceiveBufferSize
1272 );
1273 //
1274 // TPM_PhysicalEnable
1275 //
1276 ReceiveBufferSize = sizeof(ReceiveBuffer);
1277 Status = TpmMpDriver->Transmit (
1278 TpmMpDriver,
1279 TpmPhysicalEnableCommand,
1280 sizeof (TpmPhysicalEnableCommand),
1281 ReceiveBuffer,
1282 &ReceiveBufferSize
1283 );
1284 //
1285 // TPM_PhysicalSetDeactivated=FALSE
1286 //
1287 ReceiveBufferSize = sizeof(ReceiveBuffer);
1288 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1289 Status = TpmMpDriver->Transmit (
1290 TpmMpDriver,
1291 TpmPhysicalSetDeactivatedCommand,
1292 sizeof (TpmPhysicalSetDeactivatedCommand),
1293 ReceiveBuffer,
1294 &ReceiveBufferSize
1295 );
1296 gRT->ResetSystem (
1297 EfiResetWarm,
1298 EFI_SUCCESS,
1299 0,
1300 NULL
1301 );
1302 }
1303 if (Data == 0xF0)
1304 {
1305 //
1306 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1307 //
1308 ReceiveBufferSize = sizeof(ReceiveBuffer);
1309 TpmSetOwnerInstallCommand [10] = 0x01;
1310 Status = TpmMpDriver->Transmit (
1311 TpmMpDriver,
1312 TpmSetOwnerInstallCommand,
1313 sizeof (TpmSetOwnerInstallCommand),
1314 ReceiveBuffer,
1315 &ReceiveBufferSize
1316 );
1317 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
1318 }
1319 //
1320 // Deassert Physical Presence
1321 //
1322 TpmPhysicalPresenceCommand [11] = 0x10;
1323 ReceiveBufferSize = sizeof(ReceiveBuffer);
1324 Status = TpmMpDriver->Transmit (
1325 TpmMpDriver,
1326 TpmPhysicalPresenceCommand,
1327 sizeof (TpmPhysicalPresenceCommand),
1328 ReceiveBuffer,
1329 &ReceiveBufferSize
1330 );
1331 }
1332 }
1333
1334 return;
1335 }
1336
1337 /**
1338
1339 Initializes manufacturing and config mode setting.
1340
1341 **/
1342 VOID
1343 InitMfgAndConfigModeStateVar()
1344 {
1345 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1346 VOID *HobList;
1347 UINT16 State;
1348
1349 //
1350 // Variable initialization
1351 //
1352 State = FALSE;
1353
1354 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1355 if (HobList != NULL) {
1356 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1357
1358 //
1359 // Check if in Manufacturing mode
1360 //
1361 if ( !CompareMem (
1362 &BootModeBuffer->SetupName,
1363 MANUFACTURE_SETUP_NAME,
1364 StrSize (MANUFACTURE_SETUP_NAME)
1365 ) ) {
1366 mMfgMode = TRUE;
1367 }
1368
1369 //
1370 // Check if in safe mode
1371 //
1372 if ( !CompareMem (
1373 &BootModeBuffer->SetupName,
1374 SAFE_SETUP_NAME,
1375 StrSize (SAFE_SETUP_NAME)
1376 ) ) {
1377 State = TRUE;
1378 }
1379 }
1380
1381 }
1382
1383 /**
1384
1385 Initializes manufacturing and config mode setting.
1386
1387 **/
1388 VOID
1389 InitPlatformBootMode()
1390 {
1391 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1392 VOID *HobList;
1393
1394 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1395 if (HobList != NULL) {
1396 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1397 mPlatformBootMode = BootModeBuffer->PlatformBootMode;
1398 }
1399 }
1400
1401 /**
1402
1403 Initializes ITK.
1404
1405 **/
1406 VOID
1407 InitItk(
1408 )
1409 {
1410 EFI_STATUS Status;
1411 UINT16 ItkModBiosState;
1412 UINT8 Value;
1413 UINTN DataSize;
1414 UINT32 Attributes;
1415
1416 //
1417 // Setup local variable according to ITK variable
1418 //
1419 //
1420 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1421 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1422 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1423 //
1424 DataSize = sizeof (Value);
1425 Status = gRT->GetVariable (
1426 ITK_BIOS_MOD_VAR_NAME,
1427 &gItkDataVarGuid,
1428 &Attributes,
1429 &DataSize,
1430 &Value
1431 );
1432 if (Status == EFI_NOT_FOUND) {
1433 //
1434 // Variable not found, hasn't been initialized, intialize to 0
1435 //
1436 Value=0x00;
1437 //
1438 // Write variable to flash.
1439 //
1440 gRT->SetVariable (
1441 ITK_BIOS_MOD_VAR_NAME,
1442 &gItkDataVarGuid,
1443 EFI_VARIABLE_RUNTIME_ACCESS |
1444 EFI_VARIABLE_NON_VOLATILE |
1445 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1446 sizeof (Value),
1447 &Value
1448 );
1449
1450 }
1451 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
1452 if (Value == 0x00) {
1453 ItkModBiosState = 0x00;
1454 } else {
1455 ItkModBiosState = 0x01;
1456 }
1457 gRT->SetVariable (
1458 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
1459 &gEfiNormalSetupGuid,
1460 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1461 2,
1462 (void *)&ItkModBiosState
1463 );
1464 }
1465 }
1466
1467 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1468
1469 /**
1470
1471 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1472
1473 **/
1474 STATIC
1475 VOID
1476 InitFirmwareId(
1477 )
1478 {
1479 EFI_STATUS Status;
1480 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
1481
1482 //
1483 // First try writing the variable without a password in case we are
1484 // upgrading from a BIOS without password protection on the FirmwareId
1485 //
1486 Status = gRT->SetVariable(
1487 (CHAR16 *)&gFirmwareIdName,
1488 &gFirmwareIdGuid,
1489 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1490 EFI_VARIABLE_RUNTIME_ACCESS,
1491 sizeof( FIRMWARE_ID ) - 1,
1492 FIRMWARE_ID
1493 );
1494
1495 if (Status == EFI_INVALID_PARAMETER) {
1496
1497 //
1498 // Since setting the firmware id without the password failed,
1499 // a password must be required.
1500 //
1501 Status = gRT->SetVariable(
1502 (CHAR16 *)&FirmwareIdNameWithPassword,
1503 &gFirmwareIdGuid,
1504 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1505 EFI_VARIABLE_RUNTIME_ACCESS,
1506 sizeof( FIRMWARE_ID ) - 1,
1507 FIRMWARE_ID
1508 );
1509 }
1510 }
1511 #endif
1512
1513 VOID
1514 UpdateDVMTSetup(
1515 )
1516 {
1517 //
1518 // Workaround to support IIA bug.
1519 // IIA request to change option value to 4, 5 and 7 relatively
1520 // instead of 1, 2, and 3 which follow Lakeport Specs.
1521 // Check option value, temporary hardcode GraphicsDriverMemorySize
1522 // Option value to fulfill IIA requirment. So that user no need to
1523 // load default and update setupvariable after update BIOS.
1524 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1525 // *This is for broadwater and above product only.
1526 //
1527
1528 SYSTEM_CONFIGURATION SystemConfiguration;
1529 UINTN VarSize;
1530 EFI_STATUS Status;
1531
1532 VarSize = sizeof(SYSTEM_CONFIGURATION);
1533 Status = gRT->GetVariable(
1534 NORMAL_SETUP_NAME,
1535 &gEfiNormalSetupGuid,
1536 NULL,
1537 &VarSize,
1538 &SystemConfiguration
1539 );
1540
1541 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
1542 switch (SystemConfiguration.GraphicsDriverMemorySize){
1543 case 1:
1544 SystemConfiguration.GraphicsDriverMemorySize = 4;
1545 break;
1546 case 2:
1547 SystemConfiguration.GraphicsDriverMemorySize = 5;
1548 break;
1549 case 3:
1550 SystemConfiguration.GraphicsDriverMemorySize = 7;
1551 break;
1552 default:
1553 break;
1554 }
1555
1556 Status = gRT->SetVariable (
1557 NORMAL_SETUP_NAME,
1558 &gEfiNormalSetupGuid,
1559 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
1560 sizeof(SYSTEM_CONFIGURATION),
1561 &SystemConfiguration
1562 );
1563 }
1564 }
1565
1566 VOID
1567 InitPlatformUsbPolicy (
1568 VOID
1569 )
1570
1571 {
1572 EFI_HANDLE Handle;
1573 EFI_STATUS Status;
1574
1575 Handle = NULL;
1576
1577 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
1578 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
1579 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
1580 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
1581 } else {
1582 mUsbPolicyData.UsbEmulationSize = 0;
1583 }
1584 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
1585 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
1586
1587 //
1588 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1589 //
1590 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
1591
1592 //
1593 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1594 //
1595 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
1596
1597 //
1598 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1599 //
1600 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
1601
1602 //
1603 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1604 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1605 mUsbPolicyData.LpcAcpiBase = 0x40;
1606 mUsbPolicyData.AcpiTimerReg = 0x08;
1607
1608 //
1609 // Set for reduce usb post time
1610 //
1611 mUsbPolicyData.UsbTimeTue = 0x00;
1612 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
1613 mUsbPolicyData.EnumWaitPortStableStall = 100;
1614
1615
1616 Status = gBS->InstallProtocolInterface (
1617 &Handle,
1618 &gUsbPolicyGuid,
1619 EFI_NATIVE_INTERFACE,
1620 &mUsbPolicyData
1621 );
1622 ASSERT_EFI_ERROR(Status);
1623
1624 }
1625
1626 UINT8
1627 ReadCmosBank1Byte (
1628 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1629 IN UINT8 Index
1630 )
1631 {
1632 UINT8 Data;
1633
1634 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
1635 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
1636 return Data;
1637 }
1638
1639 VOID
1640 WriteCmosBank1Byte (
1641 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1642 IN UINT8 Index,
1643 IN UINT8 Data
1644 )
1645 {
1646 CpuIo->Io.Write (
1647 CpuIo,
1648 EfiCpuIoWidthUint8,
1649 0x72,
1650 1,
1651 &Index
1652 );
1653 CpuIo->Io.Write (
1654 CpuIo,
1655 EfiCpuIoWidthUint8,
1656 0x73,
1657 1,
1658 &Data
1659 );
1660 }
1661
EFI Development Kit II mirror for PVE