Set RTC initial time to be BIOS Release time.
[mirror_edk2.git] / Vlv2TbltDevicePkg / PlatformDxe / Platform.c
1 /** @file
2
3 Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
4
5
6 This program and the accompanying materials are licensed and made available under
7
8 the terms and conditions of the BSD License that accompanies this distribution.
9
10 The full text of the license may be found at
11
12 http://opensource.org/licenses/bsd-license.php.
13
14
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20
21
22
23 Module Name:
24
25
26 Platform.c
27
28 Abstract:
29
30 Platform Initialization Driver.
31
32
33 --*/
34
35 #include "PlatformDxe.h"
36 #include "Platform.h"
37 #include "PchCommonDefinitions.h"
38 #include <Protocol/UsbPolicy.h>
39 #include <Protocol/PchPlatformPolicy.h>
40 #include <Protocol/TpmMp.h>
41 #include <Protocol/CpuIo2.h>
42 #include <Library/S3BootScriptLib.h>
43 #include <Guid/PciLanInfo.h>
44 #include <Guid/ItkData.h>
45 #include <Library/PciLib.h>
46 #include <PlatformBootMode.h>
47 #include <Guid/EventGroup.h>
48 #include <Guid/Vlv2Variable.h>
49 #include <Protocol/GlobalNvsArea.h>
50 #include <Protocol/IgdOpRegion.h>
51 #include <Library/PcdLib.h>
52
53 //
54 // VLV2 GPIO GROUP OFFSET
55 //
56 #define GPIO_SCORE_OFFSET 0x0000
57 #define GPIO_NCORE_OFFSET 0x1000
58 #define GPIO_SSUS_OFFSET 0x2000
59
60 typedef struct {
61 UINT32 offset;
62 UINT32 val;
63 } CFIO_PNP_INIT;
64
65 GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
66 {
67 // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
68 GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
69 GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
70 };
71
72
73 EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
74 EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
75 SYSTEM_CONFIGURATION mSystemConfiguration;
76 SYSTEM_PASSWORDS mSystemPassword;
77 EFI_HANDLE mImageHandle;
78 BOOLEAN mMfgMode = FALSE;
79 VOID *mDxePlatformStringPack;
80 UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
81 extern CHAR16 gItkDataVarName[];
82
83
84 EFI_PLATFORM_INFO_HOB mPlatformInfo;
85 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
86 EFI_EVENT mReadyToBootEvent;
87
88 UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
89 UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
90 UINT32 mSubsystemVidDid;
91 UINT32 mSubsystemAudioVidDid;
92
93 UINTN mPciLanCount = 0;
94 VOID *mPciLanInfo = NULL;
95 UINTN SpiBase;
96
97 static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
98 ProgramToneFrequency,
99 GenerateBeepTone
100 };
101
102 EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};
103
104
105 CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
106 {
107 {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
108 {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
109 {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
110 {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
111 {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
112 {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
113 {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
114 {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
115 {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
116 {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
117 {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
118 {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
119 {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
120 {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
121 {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
122 {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
123 {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
124 {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
125 };
126
127 VOID
128 EfiOrMem (
129 IN VOID *Destination,
130 IN VOID *Source,
131 IN UINTN Length
132 );
133
134 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
135 STATIC
136 VOID
137 InitFirmwareId();
138 #endif
139
140
141 VOID
142 InitializeClockRouting(
143 );
144
145 VOID
146 InitializeSlotInfo (
147 );
148
149 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
150 VOID
151 InitializeSensorInfoVariable (
152 );
153 #endif
154
155 VOID
156 InitTcoReset (
157 );
158
159 VOID
160 InitExI ();
161
162 VOID
163 InitItk();
164
165 VOID
166 InitPlatformBootMode();
167
168 VOID
169 InitMfgAndConfigModeStateVar();
170
171 VOID
172 InitPchPlatformPolicy (
173 IN EFI_PLATFORM_INFO_HOB *PlatformInfo
174 );
175
176 VOID
177 InitVlvPlatformPolicy (
178 );
179
180 VOID
181 InitSioPlatformPolicy(
182 );
183
184 VOID
185 PchInitBeforeBoot(
186 );
187
188 VOID
189 UpdateDVMTSetup(
190 );
191
192 VOID
193 InitPlatformUsbPolicy (
194 VOID
195 );
196
197 VOID
198 InitRC6Policy(
199 VOID
200 );
201
202
203 VOID
204 TristateLpcGpioConfig (
205 IN UINT32 Gpio_Mmio_Offset,
206 IN UINT32 Gpio_Pin_Num,
207 GPIO_CONF_PAD_INIT* Gpio_Conf_Data
208 )
209
210 {
211 UINT32 index;
212 UINT32 mmio_conf0;
213 UINT32 mmio_padval;
214 PAD_CONF0 conf0_val;
215 PAD_VAL pad_val;
216
217 //
218 // GPIO WELL -- Memory base registers
219 //
220
221 //
222 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
223 // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
224 //
225
226 for(index=0; index < Gpio_Pin_Num; index++)
227 {
228 //
229 // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
230 //
231 mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
232 mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
233
234 #ifdef EFI_DEBUG
235 DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
236
237 #endif
238 DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
239 Gpio_Conf_Data[index].usage,
240 Gpio_Conf_Data[index].func,
241 Gpio_Conf_Data[index].int_type,
242 Gpio_Conf_Data[index].pull,
243 mmio_conf0));
244
245 //
246 // Step 1: PadVal Programming
247 //
248 pad_val.dw = MmioRead32(mmio_padval);
249
250 //
251 // Config PAD_VAL only for GPIO (Non-Native) Pin
252 //
253 if(Native != Gpio_Conf_Data[index].usage)
254 {
255 pad_val.dw &= ~0x6; // Clear bits 1:2
256 pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
257
258 //
259 // set GPO default value
260 //
261 if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
262 {
263 pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
264 }
265 }
266
267
268 DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
269
270 MmioWrite32(mmio_padval, pad_val.dw);
271
272 //
273 // Step 2: CONF0 Programming
274 // Read GPIO default CONF0 value, which is assumed to be default value after reset.
275 //
276 conf0_val.dw = MmioRead32(mmio_conf0);
277
278 //
279 // Set Function #
280 //
281 conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
282
283 if(GPO == Gpio_Conf_Data[index].usage)
284 {
285 //
286 // If used as GPO, then internal pull need to be disabled
287 //
288 conf0_val.r.Pull_assign = 0; // Non-pull
289 }
290 else
291 {
292 //
293 // Set PullUp / PullDown
294 //
295 if(P_20K_H == Gpio_Conf_Data[index].pull)
296 {
297 conf0_val.r.Pull_assign = 0x1; // PullUp
298 conf0_val.r.Pull_strength = 0x2;// 20K
299 }
300 else if(P_20K_L == Gpio_Conf_Data[index].pull)
301 {
302 conf0_val.r.Pull_assign = 0x2; // PullDown
303 conf0_val.r.Pull_strength = 0x2;// 20K
304 }
305 else if(P_NONE == Gpio_Conf_Data[index].pull)
306 {
307 conf0_val.r.Pull_assign = 0; // Non-pull
308 }
309 else
310 {
311 ASSERT(FALSE); // Invalid value
312 }
313 }
314
315 //
316 // Set INT Trigger Type
317 //
318 conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
319
320 //
321 // Set INT Trigger Type
322 //
323 if(TRIG_ == Gpio_Conf_Data[index].int_type)
324 {
325 //
326 // Interrupt not capable, clear bits 27:24
327 //
328 }
329 else
330 {
331 conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
332 }
333
334 DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
335
336 //
337 // Write back the targeted GPIO config value according to platform (board) GPIO setting
338 //
339 MmioWrite32 (mmio_conf0, conf0_val.dw);
340 }
341
342 // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
343 // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
344 //
345 }
346
347 VOID
348 EFIAPI
349 SpiBiosProtectionFunction(
350 EFI_EVENT Event,
351 VOID *Context
352 )
353 {
354
355 UINTN mPciD31F0RegBase;
356 UINTN BiosFlaLower = 0;
357 UINTN BiosFlaLimit = 0x7fffff;
358
359 BiosFlaLower = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
360
361
362 mPciD31F0RegBase = MmPciAddress (0,
363 DEFAULT_PCI_BUS_NUMBER_PCH,
364 PCI_DEVICE_NUMBER_PCH_LPC,
365 PCI_FUNCTION_NUMBER_PCH_LPC,
366 0
367 );
368 SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
369
370 //
371 //Set SMM_BWP, WPD and LE bit
372 //
373 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
374 MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
375 MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
376
377 //
378 //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
379 //
380 if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
381 (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
382 //
383 //Already locked. we could take no action here
384 //
385 DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
386 return;
387 }
388
389 //
390 //Set PR0
391 //
392 MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
393 B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
394 (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit>>12)<<16));
395
396 //
397 //Lock down PR0
398 //
399 MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
400
401 //
402 // Verify if it's really locked.
403 //
404 if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
405 DEBUG((EFI_D_ERROR, "Failed to lock down PR0.\n"));
406 }
407
408 return;
409
410 }
411
412 VOID
413 EFIAPI
414 InitPciDevPME (
415 EFI_EVENT Event,
416 VOID *Context
417 )
418 {
419 UINTN VarSize;
420 EFI_STATUS Status;
421
422 VarSize = sizeof(SYSTEM_CONFIGURATION);
423 Status = gRT->GetVariable(
424 NORMAL_SETUP_NAME,
425 &gEfiNormalSetupGuid,
426 NULL,
427 &VarSize,
428 &mSystemConfiguration
429 );
430
431 //
432 //Program HDA PME_EN
433 //
434 PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
435
436 //
437 //Program SATA PME_EN
438 //
439 PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
440
441 DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
442 if (mSystemConfiguration.EhciPllCfgEnable != 1) {
443 //
444 //Program EHCI PME_EN
445 //
446 PchMmPci32Or (
447 0,
448 0,
449 PCI_DEVICE_NUMBER_PCH_USB,
450 PCI_FUNCTION_NUMBER_PCH_EHCI,
451 R_PCH_EHCI_PWR_CNTL_STS,
452 B_PCH_EHCI_PWR_CNTL_STS_PME_EN
453 );
454 }
455 {
456 UINTN EhciPciMmBase;
457 UINT32 Buffer32 = 0;
458
459 EhciPciMmBase = MmPciAddress (0,
460 0,
461 PCI_DEVICE_NUMBER_PCH_USB,
462 PCI_FUNCTION_NUMBER_PCH_EHCI,
463 0
464 );
465 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
466 Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
467 DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
468 }
469 }
470
471 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
472
473 #endif
474
475
476 EFI_STATUS
477 EFIAPI
478 TristateLpcGpioS0i3Config (
479 UINT32 Gpio_Mmio_Offset,
480 UINT32 Gpio_Pin_Num,
481 CFIO_PNP_INIT* Gpio_Conf_Data
482 )
483 {
484
485 UINT32 index;
486 UINT32 mmio_reg;
487 UINT32 mmio_val;
488
489 DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
490
491 for(index=0; index < Gpio_Pin_Num; index++)
492 {
493 mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
494
495 MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
496 mmio_val = 0;
497 mmio_val = MmioRead32(mmio_reg);
498
499 DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
500 }
501
502 return EFI_SUCCESS;
503 }
504
505
506 EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;
507
508 /**
509 Event Notification during exit boot service to enabel ACPI mode
510
511 Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
512
513 Clear all ACPI event status and disable all ACPI events
514 Disable PM sources except power button
515 Clear status bits
516
517 Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
518
519 Update EC to disable SMI and enable SCI
520
521 Enable SCI
522
523 Enable PME_B0_EN in GPE0a_EN
524
525 @param Event - EFI Event Handle
526 @param Context - Pointer to Notify Context
527
528 @retval Nothing
529
530 **/
531 VOID
532 EFIAPI
533 EnableAcpiCallback (
534 IN EFI_EVENT Event,
535 IN VOID *Context
536 )
537 {
538 UINT32 RegData32;
539 UINT16 Pm1Cnt;
540 UINT16 AcpiBase;
541 UINT32 Gpe0aEn;
542
543 AcpiBase = MmioRead16 (
544 PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
545 PCI_DEVICE_NUMBER_PCH_LPC,
546 PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
547 ) & B_PCH_LPC_ACPI_BASE_BAR;
548
549 DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
550
551 //
552 // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
553 //
554 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
555 RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
556 IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
557
558 RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
559 RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
560 IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
561
562 //
563 // Disable PM sources except power button
564 // power button is enabled only for PCAT. Disabled it on Tablet platform
565 //
566
567 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
568 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
569
570 //
571 // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
572 // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
573 //
574 IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
575 IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
576
577 RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
578 RegData32 &= ~(BIT7);
579 IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
580
581 //
582 // Enable SCI
583 //
584 Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
585 Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
586 IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
587
588 IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
589
590 //
591 // Enable PME_B0_EN in GPE0a_EN
592 // Caution: Enable PME_B0_EN must be placed after enabling SCI.
593 // Otherwise, USB PME could not be handled as SMI event since no handler is there.
594 //
595 Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
596 Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
597 IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
598
599 }
600
601 /**
602
603 Routine Description:
604
605 This is the standard EFI driver point for the Driver. This
606 driver is responsible for setting up any platform specific policy or
607 initialization information.
608
609 @param ImageHandle Handle for the image of this driver.
610 @param SystemTable Pointer to the EFI System Table.
611
612 @retval EFI_SUCCESS Policy decisions set.
613
614 **/
615 EFI_STATUS
616 EFIAPI
617 InitializePlatform (
618 IN EFI_HANDLE ImageHandle,
619 IN EFI_SYSTEM_TABLE *SystemTable
620 )
621 {
622 EFI_STATUS Status;
623 UINTN VarSize;
624 EFI_HANDLE Handle = NULL;
625 EFI_EVENT mEfiExitBootServicesEvent;
626 EFI_EVENT RtcEvent;
627 VOID *RtcCallbackReg = NULL;
628
629 mImageHandle = ImageHandle;
630
631 Status = gBS->InstallProtocolInterface (
632 &Handle,
633 &gEfiSpeakerInterfaceProtocolGuid,
634 EFI_NATIVE_INTERFACE,
635 &mSpeakerInterface
636 );
637
638 Status = gBS->LocateProtocol (
639 &gEfiPciRootBridgeIoProtocolGuid,
640 NULL,
641 (VOID **) &mPciRootBridgeIo
642 );
643 ASSERT_EFI_ERROR (Status);
644
645 VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
646 Status = gRT->GetVariable(
647 L"PlatformInfo",
648 &gEfiVlv2VariableGuid,
649 NULL,
650 &VarSize,
651 &mPlatformInfo
652 );
653
654 //
655 // Initialize Product Board ID variable
656 //
657 InitMfgAndConfigModeStateVar();
658 InitPlatformBootMode();
659
660 //
661 // Install Observable protocol
662 //
663 InitializeObservableProtocol();
664
665
666 VarSize = sizeof(SYSTEM_CONFIGURATION);
667 Status = gRT->GetVariable(
668 NORMAL_SETUP_NAME,
669 &gEfiNormalSetupGuid,
670 NULL,
671 &VarSize,
672 &mSystemConfiguration
673 );
674
675
676 Status = EfiCreateEventReadyToBootEx (
677 TPL_CALLBACK,
678 ReadyToBootFunction,
679 NULL,
680 &mReadyToBootEvent
681 );
682
683 //
684 // Create a ReadyToBoot Event to run the PME init process
685 //
686 Status = EfiCreateEventReadyToBootEx (
687 TPL_CALLBACK,
688 InitPciDevPME,
689 NULL,
690 &mReadyToBootEvent
691 );
692 //
693 // Create a ReadyToBoot Event to run enable PR0 and lock down
694 //
695 if(mSystemConfiguration.SpiRwProtect==1) {
696 Status = EfiCreateEventReadyToBootEx (
697 TPL_CALLBACK,
698 SpiBiosProtectionFunction,
699 NULL,
700 &mReadyToBootEvent
701 );
702 }
703
704 ReportStatusCodeEx (
705 EFI_PROGRESS_CODE,
706 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
707 0,
708 &gEfiCallerIdGuid,
709 NULL,
710 NULL,
711 0
712 );
713
714 #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
715 //
716 // Initialize Sensor Info variable
717 //
718 InitializeSensorInfoVariable();
719 #endif
720 InitPchPlatformPolicy(&mPlatformInfo);
721 InitVlvPlatformPolicy();
722
723 //
724 // Add usb policy
725 //
726 InitPlatformUsbPolicy();
727 InitSioPlatformPolicy();
728 InitializeClockRouting();
729 InitializeSlotInfo();
730 InitTcoReset();
731
732 //
733 //Init ExI
734 //
735 InitExI();
736
737 ReportStatusCodeEx (
738 EFI_PROGRESS_CODE,
739 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
740 0,
741 &gEfiCallerIdGuid,
742 NULL,
743 NULL,
744 0
745 );
746
747 //
748 // Install PCI Bus Driver Hook
749 //
750 PciBusDriverHook();
751
752 InitItk();
753
754 ReportStatusCodeEx (
755 EFI_PROGRESS_CODE,
756 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
757 0,
758 &gEfiCallerIdGuid,
759 NULL,
760 NULL,
761 0
762 );
763
764
765 //
766 // Initialize Password States and Callbacks
767 //
768 PchInitBeforeBoot();
769
770 #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
771
772 #endif
773
774 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
775 //
776 // Re-write Firmware ID if it is changed
777 //
778 InitFirmwareId();
779 #endif
780
781 ReportStatusCodeEx (
782 EFI_PROGRESS_CODE,
783 EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
784 0,
785 &gEfiCallerIdGuid,
786 NULL,
787 NULL,
788 0
789 );
790
791
792 Status = gBS->CreateEventEx (
793 EVT_NOTIFY_SIGNAL,
794 TPL_NOTIFY,
795 EnableAcpiCallback,
796 NULL,
797 &gEfiEventExitBootServicesGuid,
798 &mEfiExitBootServicesEvent
799 );
800
801 //
802 // Adjust RTC deafult time to be BIOS-built time.
803 //
804 Status = gBS->CreateEvent (
805 EVT_NOTIFY_SIGNAL,
806 TPL_CALLBACK,
807 AdjustDefaultRtcTimeCallback,
808 NULL,
809 &RtcEvent
810 );
811 if (!EFI_ERROR (Status)) {
812 Status = gBS->RegisterProtocolNotify (
813 &gExitPmAuthProtocolGuid,
814 RtcEvent,
815 &RtcCallbackReg
816 );
817
818 }
819
820 return EFI_SUCCESS;
821 }
822
823 /**
824 Source Or Destination with Length bytes.
825
826 @param[in] Destination Target memory
827 @param[in] Source Source memory
828 @param[in] Length Number of bytes
829
830 @retval None
831
832 **/
833 VOID
834 EfiOrMem (
835 IN VOID *Destination,
836 IN VOID *Source,
837 IN UINTN Length
838 )
839 {
840 CHAR8 *Destination8;
841 CHAR8 *Source8;
842
843 if (Source < Destination) {
844 Destination8 = (CHAR8 *) Destination + Length - 1;
845 Source8 = (CHAR8 *) Source + Length - 1;
846 while (Length--) {
847 *(Destination8--) |= *(Source8--);
848 }
849 } else {
850 Destination8 = (CHAR8 *) Destination;
851 Source8 = (CHAR8 *) Source;
852 while (Length--) {
853 *(Destination8++) |= *(Source8++);
854 }
855 }
856 }
857
858 VOID
859 PchInitBeforeBoot()
860 {
861 //
862 // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
863 //
864 S3BootScriptSaveMemWrite (
865 EfiBootScriptWidthUint32,
866 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
867 1,
868 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
869
870 S3BootScriptSaveMemWrite (
871 EfiBootScriptWidthUint32,
872 (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
873 1,
874 (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
875
876 S3BootScriptSaveMemWrite (
877 EfiBootScriptWidthUint16,
878 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
879 1,
880 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
881
882 S3BootScriptSaveMemWrite (
883 EfiBootScriptWidthUint16,
884 (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
885 1,
886 (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
887
888 //
889 // Saved MTPMC_1 for S3 resume.
890 //
891 S3BootScriptSaveMemWrite (
892 EfiBootScriptWidthUint32,
893 (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
894 1,
895 (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
896 return;
897 }
898
899 VOID
900 EFIAPI
901 ReadyToBootFunction (
902 EFI_EVENT Event,
903 VOID *Context
904 )
905 {
906 EFI_STATUS Status;
907 EFI_ISA_ACPI_PROTOCOL *IsaAcpi;
908 EFI_ISA_ACPI_DEVICE_ID IsaDevice;
909 UINTN Size;
910 UINT16 State;
911 EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;
912 EFI_CPU_IO_PROTOCOL *CpuIo;
913 UINT8 Data;
914 UINT8 ReceiveBuffer [64];
915 UINT32 ReceiveBufferSize;
916
917 UINT8 TpmForceClearCommand [] = {0x00, 0xC1,
918 0x00, 0x00, 0x00, 0x0A,
919 0x00, 0x00, 0x00, 0x5D};
920 UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,
921 0x00, 0x00, 0x00, 0x0C,
922 0x40, 0x00, 0x00, 0x0A,
923 0x00, 0x00};
924 UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,
925 0x00, 0x00, 0x00, 0x0A,
926 0x00, 0x00, 0x00, 0x70};
927 UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,
928 0x00, 0x00, 0x00, 0x0A,
929 0x00, 0x00, 0x00, 0x6F};
930 UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,
931 0x00, 0x00, 0x00, 0x0B,
932 0x00, 0x00, 0x00, 0x72,
933 0x00};
934 UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,
935 0x00, 0x00, 0x00, 0x0B,
936 0x00, 0x00, 0x00, 0x71,
937 0x00};
938
939 Size = sizeof(UINT16);
940 Status = gRT->GetVariable (
941 VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,
942 &gEfiNormalSetupGuid,
943 NULL,
944 &Size,
945 &State
946 );
947
948 //
949 // Disable Floppy Controller if needed
950 //
951 Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);
952 if (!EFI_ERROR(Status) && (State == 0x00)) {
953 IsaDevice.HID = EISA_PNP_ID(0x604);
954 IsaDevice.UID = 0;
955 Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);
956 }
957
958 //
959 // save LAN info to a variable
960 //
961 if (NULL != mPciLanInfo) {
962 gRT->SetVariable (
963 L"PciLanInfo",
964 &gEfiPciLanInfoGuid,
965 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
966 mPciLanCount * sizeof(PCI_LAN_INFO),
967 mPciLanInfo
968 );
969 }
970
971 if (NULL != mPciLanInfo) {
972 gBS->FreePool (mPciLanInfo);
973 mPciLanInfo = NULL;
974 }
975
976
977 //
978 // Handle ACPI OS TPM requests here
979 //
980 Status = gBS->LocateProtocol (
981 &gEfiCpuIoProtocolGuid,
982 NULL,
983 (VOID **)&CpuIo
984 );
985 Status = gBS->LocateProtocol (
986 &gEfiTpmMpDriverProtocolGuid,
987 NULL,
988 (VOID **)&TpmMpDriver
989 );
990 if (!EFI_ERROR (Status))
991 {
992 Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);
993
994 //
995 // Clear pending ACPI TPM request indicator
996 //
997 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);
998 if (Data != 0)
999 {
1000 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);
1001
1002 //
1003 // Assert Physical Presence for these commands
1004 //
1005 TpmPhysicalPresenceCommand [11] = 0x20;
1006 ReceiveBufferSize = sizeof(ReceiveBuffer);
1007 Status = TpmMpDriver->Transmit (
1008 TpmMpDriver, TpmPhysicalPresenceCommand,
1009 sizeof (TpmPhysicalPresenceCommand),
1010 ReceiveBuffer, &ReceiveBufferSize
1011 );
1012 //
1013 // PF PhysicalPresence = TRUE
1014 //
1015 TpmPhysicalPresenceCommand [11] = 0x08;
1016 ReceiveBufferSize = sizeof(ReceiveBuffer);
1017 Status = TpmMpDriver->Transmit (
1018 TpmMpDriver, TpmPhysicalPresenceCommand,
1019 sizeof (TpmPhysicalPresenceCommand),
1020 ReceiveBuffer,
1021 &ReceiveBufferSize
1022 );
1023 if (Data == 0x01)
1024 {
1025 //
1026 // TPM_PhysicalEnable
1027 //
1028 ReceiveBufferSize = sizeof(ReceiveBuffer);
1029 Status = TpmMpDriver->Transmit (
1030 TpmMpDriver, TpmPhysicalEnableCommand,
1031 sizeof (TpmPhysicalEnableCommand),
1032 ReceiveBuffer, &ReceiveBufferSize
1033 );
1034 }
1035 if (Data == 0x02)
1036 {
1037 //
1038 // TPM_PhysicalDisable
1039 //
1040 ReceiveBufferSize = sizeof(ReceiveBuffer);
1041 Status = TpmMpDriver->Transmit (
1042 TpmMpDriver, TpmPhysicalDisableCommand,
1043 sizeof (TpmPhysicalDisableCommand),
1044 ReceiveBuffer,
1045 &ReceiveBufferSize
1046 );
1047 }
1048 if (Data == 0x03)
1049 {
1050 //
1051 // TPM_PhysicalSetDeactivated=FALSE
1052 //
1053 ReceiveBufferSize = sizeof(ReceiveBuffer);
1054 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1055 Status = TpmMpDriver->Transmit (
1056 TpmMpDriver,
1057 TpmPhysicalSetDeactivatedCommand,
1058 sizeof (TpmPhysicalSetDeactivatedCommand),
1059 ReceiveBuffer, &ReceiveBufferSize
1060 );
1061 gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);
1062 }
1063 if (Data == 0x04)
1064 {
1065 //
1066 // TPM_PhysicalSetDeactivated=TRUE
1067 //
1068 ReceiveBufferSize = sizeof(ReceiveBuffer);
1069 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1070 Status = TpmMpDriver->Transmit (
1071 TpmMpDriver,
1072 TpmPhysicalSetDeactivatedCommand,
1073 sizeof (TpmPhysicalSetDeactivatedCommand),
1074 ReceiveBuffer,
1075 &ReceiveBufferSize
1076 );
1077 gRT->ResetSystem (
1078 EfiResetWarm,
1079 EFI_SUCCESS,
1080 0,
1081 NULL
1082 );
1083 }
1084 if (Data == 0x05)
1085 {
1086 //
1087 // TPM_ForceClear
1088 //
1089 ReceiveBufferSize = sizeof(ReceiveBuffer);
1090 Status = TpmMpDriver->Transmit (
1091 TpmMpDriver,
1092 TpmForceClearCommand,
1093 sizeof (TpmForceClearCommand),
1094 ReceiveBuffer,
1095 &ReceiveBufferSize
1096 );
1097 gRT->ResetSystem (
1098 EfiResetWarm,
1099 EFI_SUCCESS,
1100 0,
1101 NULL
1102 );
1103 }
1104 if (Data == 0x06)
1105 {
1106 //
1107 // TPM_PhysicalEnable
1108 //
1109 ReceiveBufferSize = sizeof(ReceiveBuffer);
1110 Status = TpmMpDriver->Transmit (
1111 TpmMpDriver,
1112 TpmPhysicalEnableCommand,
1113 sizeof (TpmPhysicalEnableCommand),
1114 ReceiveBuffer,
1115 &ReceiveBufferSize
1116 );
1117 //
1118 // TPM_PhysicalSetDeactivated=FALSE
1119 //
1120 ReceiveBufferSize = sizeof(ReceiveBuffer);
1121 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1122 Status = TpmMpDriver->Transmit (
1123 TpmMpDriver,
1124 TpmPhysicalSetDeactivatedCommand,
1125 sizeof (TpmPhysicalSetDeactivatedCommand),
1126 ReceiveBuffer,
1127 &ReceiveBufferSize
1128 );
1129 gRT->ResetSystem (
1130 EfiResetWarm,
1131 EFI_SUCCESS,
1132 0,
1133 NULL
1134 );
1135 }
1136 if (Data == 0x07)
1137 {
1138 //
1139 // TPM_PhysicalSetDeactivated=TRUE
1140 //
1141 ReceiveBufferSize = sizeof(ReceiveBuffer);
1142 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1143 Status = TpmMpDriver->Transmit (
1144 TpmMpDriver,
1145 TpmPhysicalSetDeactivatedCommand,
1146 sizeof (TpmPhysicalSetDeactivatedCommand),
1147 ReceiveBuffer,
1148 &ReceiveBufferSize
1149 );
1150 //
1151 // TPM_PhysicalDisable
1152 //
1153 ReceiveBufferSize = sizeof(ReceiveBuffer);
1154 Status = TpmMpDriver->Transmit (
1155 TpmMpDriver,
1156 TpmPhysicalDisableCommand,
1157 sizeof (TpmPhysicalDisableCommand),
1158 ReceiveBuffer,
1159 &ReceiveBufferSize
1160 );
1161 gRT->ResetSystem (
1162 EfiResetWarm,
1163 EFI_SUCCESS,
1164 0,
1165 NULL
1166 );
1167 }
1168 if (Data == 0x08)
1169 {
1170 //
1171 // TPM_SetOwnerInstall=TRUE
1172 //
1173 ReceiveBufferSize = sizeof(ReceiveBuffer);
1174 TpmSetOwnerInstallCommand [10] = 0x01;
1175 Status = TpmMpDriver->Transmit (
1176 TpmMpDriver,
1177 TpmSetOwnerInstallCommand,
1178 sizeof (TpmSetOwnerInstallCommand),
1179 ReceiveBuffer,
1180 &ReceiveBufferSize
1181 );
1182 }
1183 if (Data == 0x09)
1184 {
1185 //
1186 // TPM_SetOwnerInstall=FALSE
1187 //
1188 ReceiveBufferSize = sizeof(ReceiveBuffer);
1189 TpmSetOwnerInstallCommand [10] = 0x00;
1190 Status = TpmMpDriver->Transmit (
1191 TpmMpDriver,
1192 TpmSetOwnerInstallCommand,
1193 sizeof (TpmSetOwnerInstallCommand),
1194 ReceiveBuffer,
1195 &ReceiveBufferSize
1196 );
1197 }
1198 if (Data == 0x0A)
1199 {
1200 //
1201 // TPM_PhysicalEnable
1202 //
1203 ReceiveBufferSize = sizeof(ReceiveBuffer);
1204 Status = TpmMpDriver->Transmit (
1205 TpmMpDriver,
1206 TpmPhysicalEnableCommand,
1207 sizeof (TpmPhysicalEnableCommand),
1208 ReceiveBuffer,
1209 &ReceiveBufferSize
1210 );
1211 //
1212 // TPM_PhysicalSetDeactivated=FALSE
1213 //
1214 ReceiveBufferSize = sizeof(ReceiveBuffer);
1215 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1216 Status = TpmMpDriver->Transmit (
1217 TpmMpDriver,
1218 TpmPhysicalSetDeactivatedCommand,
1219 sizeof (TpmPhysicalSetDeactivatedCommand),
1220 ReceiveBuffer,
1221 &ReceiveBufferSize
1222 );
1223 //
1224 // Do TPM_SetOwnerInstall=TRUE on next reboot
1225 //
1226
1227 WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);
1228
1229 gRT->ResetSystem (
1230 EfiResetWarm,
1231 EFI_SUCCESS,
1232 0,
1233 NULL
1234 );
1235 }
1236 if (Data == 0x0B)
1237 {
1238 //
1239 // TPM_SetOwnerInstall=FALSE
1240 //
1241 ReceiveBufferSize = sizeof(ReceiveBuffer);
1242 TpmSetOwnerInstallCommand [10] = 0x00;
1243 Status = TpmMpDriver->Transmit (
1244 TpmMpDriver,
1245 TpmSetOwnerInstallCommand,
1246 sizeof (TpmSetOwnerInstallCommand),
1247 ReceiveBuffer,
1248 &ReceiveBufferSize
1249 );
1250 //
1251 // TPM_PhysicalSetDeactivated=TRUE
1252 //
1253 ReceiveBufferSize = sizeof(ReceiveBuffer);
1254 TpmPhysicalSetDeactivatedCommand [10] = 0x01;
1255 Status = TpmMpDriver->Transmit (
1256 TpmMpDriver,
1257 TpmPhysicalSetDeactivatedCommand,
1258 sizeof (TpmPhysicalSetDeactivatedCommand),
1259 ReceiveBuffer,
1260 &ReceiveBufferSize
1261 );
1262 //
1263 // TPM_PhysicalDisable
1264 //
1265 ReceiveBufferSize = sizeof(ReceiveBuffer);
1266 Status = TpmMpDriver->Transmit (
1267 TpmMpDriver,
1268 TpmPhysicalDisableCommand,
1269 sizeof (TpmPhysicalDisableCommand),
1270 ReceiveBuffer,
1271 &ReceiveBufferSize
1272 );
1273 gRT->ResetSystem (
1274 EfiResetWarm,
1275 EFI_SUCCESS,
1276 0,
1277 NULL
1278 );
1279 }
1280 if (Data == 0x0E)
1281 {
1282 //
1283 // TPM_ForceClear
1284 //
1285 ReceiveBufferSize = sizeof(ReceiveBuffer);
1286 Status = TpmMpDriver->Transmit (
1287 TpmMpDriver,
1288 TpmForceClearCommand,
1289 sizeof (TpmForceClearCommand),
1290 ReceiveBuffer,
1291 &ReceiveBufferSize
1292 );
1293 //
1294 // TPM_PhysicalEnable
1295 //
1296 ReceiveBufferSize = sizeof(ReceiveBuffer);
1297 Status = TpmMpDriver->Transmit (
1298 TpmMpDriver,
1299 TpmPhysicalEnableCommand,
1300 sizeof (TpmPhysicalEnableCommand),
1301 ReceiveBuffer,
1302 &ReceiveBufferSize
1303 );
1304 //
1305 // TPM_PhysicalSetDeactivated=FALSE
1306 //
1307 ReceiveBufferSize = sizeof(ReceiveBuffer);
1308 TpmPhysicalSetDeactivatedCommand [10] = 0x00;
1309 Status = TpmMpDriver->Transmit (
1310 TpmMpDriver,
1311 TpmPhysicalSetDeactivatedCommand,
1312 sizeof (TpmPhysicalSetDeactivatedCommand),
1313 ReceiveBuffer,
1314 &ReceiveBufferSize
1315 );
1316 gRT->ResetSystem (
1317 EfiResetWarm,
1318 EFI_SUCCESS,
1319 0,
1320 NULL
1321 );
1322 }
1323 if (Data == 0xF0)
1324 {
1325 //
1326 // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE
1327 //
1328 ReceiveBufferSize = sizeof(ReceiveBuffer);
1329 TpmSetOwnerInstallCommand [10] = 0x01;
1330 Status = TpmMpDriver->Transmit (
1331 TpmMpDriver,
1332 TpmSetOwnerInstallCommand,
1333 sizeof (TpmSetOwnerInstallCommand),
1334 ReceiveBuffer,
1335 &ReceiveBufferSize
1336 );
1337 WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);
1338 }
1339 //
1340 // Deassert Physical Presence
1341 //
1342 TpmPhysicalPresenceCommand [11] = 0x10;
1343 ReceiveBufferSize = sizeof(ReceiveBuffer);
1344 Status = TpmMpDriver->Transmit (
1345 TpmMpDriver,
1346 TpmPhysicalPresenceCommand,
1347 sizeof (TpmPhysicalPresenceCommand),
1348 ReceiveBuffer,
1349 &ReceiveBufferSize
1350 );
1351 }
1352 }
1353
1354 return;
1355 }
1356
1357 /**
1358
1359 Initializes manufacturing and config mode setting.
1360
1361 **/
1362 VOID
1363 InitMfgAndConfigModeStateVar()
1364 {
1365 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1366 VOID *HobList;
1367 UINT16 State;
1368
1369 //
1370 // Variable initialization
1371 //
1372 State = FALSE;
1373
1374 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1375 if (HobList != NULL) {
1376 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1377
1378 //
1379 // Check if in Manufacturing mode
1380 //
1381 if ( !CompareMem (
1382 &BootModeBuffer->SetupName,
1383 MANUFACTURE_SETUP_NAME,
1384 StrSize (MANUFACTURE_SETUP_NAME)
1385 ) ) {
1386 mMfgMode = TRUE;
1387 }
1388
1389 //
1390 // Check if in safe mode
1391 //
1392 if ( !CompareMem (
1393 &BootModeBuffer->SetupName,
1394 SAFE_SETUP_NAME,
1395 StrSize (SAFE_SETUP_NAME)
1396 ) ) {
1397 State = TRUE;
1398 }
1399 }
1400
1401 }
1402
1403 /**
1404
1405 Initializes manufacturing and config mode setting.
1406
1407 **/
1408 VOID
1409 InitPlatformBootMode()
1410 {
1411 EFI_PLATFORM_SETUP_ID *BootModeBuffer;
1412 VOID *HobList;
1413
1414 HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
1415 if (HobList != NULL) {
1416 BootModeBuffer = GET_GUID_HOB_DATA (HobList);
1417 mPlatformBootMode = BootModeBuffer->PlatformBootMode;
1418 }
1419 }
1420
1421 /**
1422
1423 Initializes ITK.
1424
1425 **/
1426 VOID
1427 InitItk(
1428 )
1429 {
1430 EFI_STATUS Status;
1431 UINT16 ItkModBiosState;
1432 UINT8 Value;
1433 UINTN DataSize;
1434 UINT32 Attributes;
1435
1436 //
1437 // Setup local variable according to ITK variable
1438 //
1439 //
1440 // Read ItkBiosModVar to determine if BIOS has been modified by ITK
1441 // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
1442 // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
1443 //
1444 DataSize = sizeof (Value);
1445 Status = gRT->GetVariable (
1446 ITK_BIOS_MOD_VAR_NAME,
1447 &gItkDataVarGuid,
1448 &Attributes,
1449 &DataSize,
1450 &Value
1451 );
1452 if (Status == EFI_NOT_FOUND) {
1453 //
1454 // Variable not found, hasn't been initialized, intialize to 0
1455 //
1456 Value=0x00;
1457 //
1458 // Write variable to flash.
1459 //
1460 gRT->SetVariable (
1461 ITK_BIOS_MOD_VAR_NAME,
1462 &gItkDataVarGuid,
1463 EFI_VARIABLE_RUNTIME_ACCESS |
1464 EFI_VARIABLE_NON_VOLATILE |
1465 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1466 sizeof (Value),
1467 &Value
1468 );
1469
1470 }
1471 if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
1472 if (Value == 0x00) {
1473 ItkModBiosState = 0x00;
1474 } else {
1475 ItkModBiosState = 0x01;
1476 }
1477 gRT->SetVariable (
1478 VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
1479 &gEfiNormalSetupGuid,
1480 EFI_VARIABLE_BOOTSERVICE_ACCESS,
1481 2,
1482 (void *)&ItkModBiosState
1483 );
1484 }
1485 }
1486
1487 #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
1488
1489 /**
1490
1491 Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
1492
1493 **/
1494 STATIC
1495 VOID
1496 InitFirmwareId(
1497 )
1498 {
1499 EFI_STATUS Status;
1500 CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
1501
1502 //
1503 // First try writing the variable without a password in case we are
1504 // upgrading from a BIOS without password protection on the FirmwareId
1505 //
1506 Status = gRT->SetVariable(
1507 (CHAR16 *)&gFirmwareIdName,
1508 &gFirmwareIdGuid,
1509 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1510 EFI_VARIABLE_RUNTIME_ACCESS,
1511 sizeof( FIRMWARE_ID ) - 1,
1512 FIRMWARE_ID
1513 );
1514
1515 if (Status == EFI_INVALID_PARAMETER) {
1516
1517 //
1518 // Since setting the firmware id without the password failed,
1519 // a password must be required.
1520 //
1521 Status = gRT->SetVariable(
1522 (CHAR16 *)&FirmwareIdNameWithPassword,
1523 &gFirmwareIdGuid,
1524 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
1525 EFI_VARIABLE_RUNTIME_ACCESS,
1526 sizeof( FIRMWARE_ID ) - 1,
1527 FIRMWARE_ID
1528 );
1529 }
1530 }
1531 #endif
1532
1533 VOID
1534 UpdateDVMTSetup(
1535 )
1536 {
1537 //
1538 // Workaround to support IIA bug.
1539 // IIA request to change option value to 4, 5 and 7 relatively
1540 // instead of 1, 2, and 3 which follow Lakeport Specs.
1541 // Check option value, temporary hardcode GraphicsDriverMemorySize
1542 // Option value to fulfill IIA requirment. So that user no need to
1543 // load default and update setupvariable after update BIOS.
1544 // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
1545 // *This is for broadwater and above product only.
1546 //
1547
1548 SYSTEM_CONFIGURATION SystemConfiguration;
1549 UINTN VarSize;
1550 EFI_STATUS Status;
1551
1552 VarSize = sizeof(SYSTEM_CONFIGURATION);
1553 Status = gRT->GetVariable(
1554 NORMAL_SETUP_NAME,
1555 &gEfiNormalSetupGuid,
1556 NULL,
1557 &VarSize,
1558 &SystemConfiguration
1559 );
1560
1561 if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
1562 switch (SystemConfiguration.GraphicsDriverMemorySize){
1563 case 1:
1564 SystemConfiguration.GraphicsDriverMemorySize = 4;
1565 break;
1566 case 2:
1567 SystemConfiguration.GraphicsDriverMemorySize = 5;
1568 break;
1569 case 3:
1570 SystemConfiguration.GraphicsDriverMemorySize = 7;
1571 break;
1572 default:
1573 break;
1574 }
1575
1576 Status = gRT->SetVariable (
1577 NORMAL_SETUP_NAME,
1578 &gEfiNormalSetupGuid,
1579 EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
1580 sizeof(SYSTEM_CONFIGURATION),
1581 &SystemConfiguration
1582 );
1583 }
1584 }
1585
1586 VOID
1587 InitPlatformUsbPolicy (
1588 VOID
1589 )
1590
1591 {
1592 EFI_HANDLE Handle;
1593 EFI_STATUS Status;
1594
1595 Handle = NULL;
1596
1597 mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;
1598 mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;
1599 if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {
1600 mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;
1601 } else {
1602 mUsbPolicyData.UsbEmulationSize = 0;
1603 }
1604 mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;
1605 mUsbPolicyData.UsbOperationMode = HIGH_SPEED;
1606
1607 //
1608 // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP
1609 //
1610 mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;
1611
1612 //
1613 // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP
1614 //
1615 mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;
1616
1617 //
1618 // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00
1619 //
1620 mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;
1621
1622 //
1623 // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,
1624 // default is Ich acpibase =0x040. acpitimerreg=0x08.
1625 mUsbPolicyData.LpcAcpiBase = 0x40;
1626 mUsbPolicyData.AcpiTimerReg = 0x08;
1627
1628 //
1629 // Set for reduce usb post time
1630 //
1631 mUsbPolicyData.UsbTimeTue = 0x00;
1632 mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH
1633 mUsbPolicyData.EnumWaitPortStableStall = 100;
1634
1635
1636 Status = gBS->InstallProtocolInterface (
1637 &Handle,
1638 &gUsbPolicyGuid,
1639 EFI_NATIVE_INTERFACE,
1640 &mUsbPolicyData
1641 );
1642 ASSERT_EFI_ERROR(Status);
1643
1644 }
1645
1646 UINT8
1647 ReadCmosBank1Byte (
1648 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1649 IN UINT8 Index
1650 )
1651 {
1652 UINT8 Data;
1653
1654 CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
1655 CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
1656 return Data;
1657 }
1658
1659 VOID
1660 WriteCmosBank1Byte (
1661 IN EFI_CPU_IO_PROTOCOL *CpuIo,
1662 IN UINT8 Index,
1663 IN UINT8 Data
1664 )
1665 {
1666 CpuIo->Io.Write (
1667 CpuIo,
1668 EfiCpuIoWidthUint8,
1669 0x72,
1670 1,
1671 &Index
1672 );
1673 CpuIo->Io.Write (
1674 CpuIo,
1675 EfiCpuIoWidthUint8,
1676 0x73,
1677 1,
1678 &Data
1679 );
1680 }
1681