Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.c

   1
   2 /*++
   3
   4 Copyright (c)  1999  - 2014, Intel Corporation. All rights reserved
   5
   6   This program and the accompanying materials are licensed and made available under
   7   the terms and conditions of the BSD License that accompanies this distribution.
   8   The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php.
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14
  15
  16 Module Name:
  17
  18   VlvPlatformInit.c
  19
  20 Abstract:
  21
  22   This is the driver that initializes the Intel ValleyView.
  23
  24 --*/
  25
  26 #include "VlvPlatformInit.h"
  27 #include <Protocol/VlvPlatformPolicy.h>
  28
  29 extern DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;
  30 UINT64            GTTMMADR;
  31
  32 DXE_VLV_PLATFORM_POLICY_PROTOCOL  *DxePlatformSaPolicy;
  33
  34 /**
  35   "Poll Status" for GT Readiness
  36
  37  @param  Base             Base address of MMIO
  38  @param  Offset           MMIO Offset
  39  @param  Mask             Mask
  40  @param  Result           Value to wait for
  41
  42  @retval None
  43
  44 **/
  45 VOID
  46 PollGtReady_hang (
  47   UINT64 Base,
  48   UINT32 Offset,
  49   UINT32 Mask,
  50   UINT32 Result
  51   )
  52 {
  53   UINT32  GtStatus;
  54
  55   //
  56   // Register read
  57   //
  58   GtStatus = MmioRead32 ((UINTN)Base+ Offset);
  59
  60   while (((GtStatus & Mask) != Result)) {
  61
  62     GtStatus = MmioRead32 ((UINTN)Base + Offset);
  63   }
  64
  65 }
  66
  67 /**
  68   Do Post GT PM Init Steps after VBIOS Initialization.
  69
  70   @param Event             A pointer to the Event that triggered the callback.
  71   @param Context           A pointer to private data registered with the callback function.
  72
  73   @retval EFI_SUCCESS        GC_TODO
  74
  75
  76 **/
  77 EFI_STATUS
  78 EFIAPI
  79 PostPmInitCallBack (
  80   IN EFI_EVENT Event,
  81   IN VOID      *Context
  82   )
  83 {
  84   UINT64      OriginalGTTMMADR;
  85   UINT32      LoGTBaseAddress;
  86   UINT32      HiGTBaseAddress;
  87
  88   //
  89   // Enable Bus Master, I/O and Memory access on 0:2:0
  90   //
  91   PciOr8 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_CMD), (BIT2 | BIT1));
  92
  93   //
  94   // only 32bit read/write is legal for device 0:2:0
  95   //
  96   OriginalGTTMMADR  = (UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR));
  97   OriginalGTTMMADR  = LShiftU64 ((UINT64) PciRead32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR + 4)), 32) | (OriginalGTTMMADR);
  98
  99   //
 100   // 64bit GTTMADR does not work for S3 save script table since it is executed in PEIM phase
 101   // Program temporarily 32bits GTTMMADR for POST and S3 resume
 102   //
 103   LoGTBaseAddress                   = (UINT32) (GTTMMADR & 0xFFFFFFFF);
 104   HiGTBaseAddress                   = (UINT32) RShiftU64 ((GTTMMADR & 0xFFFFFFFF00000000), 32);
 105   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
 106   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
 107
 108
 109
 110   //
 111   // Restore original GTTMMADR
 112   //
 113   LoGTBaseAddress                   = (UINT32) (OriginalGTTMMADR & 0xFFFFFFFF);
 114   HiGTBaseAddress                   = (UINT32) RShiftU64 ((OriginalGTTMMADR & 0xFFFFFFFF00000000), 32);
 115
 116   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR), LoGTBaseAddress);
 117   S3PciWrite32(PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_GTTMMADR+4), HiGTBaseAddress);
 118
 119
 120   //
 121   // Lock the following registers, GGC, BDSM, BGSM
 122   //
 123   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_MGGC_OFFSET), LockBit);
 124   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_BSM_OFFSET), LockBit);
 125   PciOr32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0,IGD_R_BGSM), LockBit);
 126
 127   gBS->CloseEvent (Event);
 128
 129   //
 130   // Return final status
 131   //
 132   return EFI_SUCCESS;
 133 }
 134
 135 /**
 136
 137   Routine Description:
 138
 139   Initialize GT Post Routines.
 140
 141   @param ImageHandle              Handle for the image of this driver
 142   @param DxePlatformSaPolicy      SA DxePlatformPolicy protocol
 143
 144   @retval EFI_SUCCESS             GT POST initialization complete
 145
 146 **/
 147 EFI_STATUS
 148 IgdPmHook (
 149   IN EFI_HANDLE                      ImageHandle,
 150   IN DXE_VLV_PLATFORM_POLICY_PROTOCOL *DxePlatformSaPolicy
 151   )
 152 {
 153
 154   EFI_EVENT             mConOutEvent;
 155   VOID                  *gConOutNotifyReg;
 156
 157   EFI_STATUS            Status;
 158
 159   EFI_PHYSICAL_ADDRESS  MemBaseAddress;
 160   UINT32                LoGTBaseAddress;
 161   UINT32                HiGTBaseAddress;
 162
 163   GTTMMADR    = 0;
 164   Status      = EFI_SUCCESS;
 165
 166   //
 167   // If device 0:2:0 (Internal Graphics Device, or GT) is enabled, then Program GTTMMADR,
 168   //
 169   if (PciRead16(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_VID))  != 0xFFFF) {
 170
 171     ASSERT (gDS!=NULL);
 172
 173     //
 174     // Enable Bus Master, I/O and Memory access on 0:2:0
 175     //
 176     PciOr8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD), (BIT2 | BIT1 | BIT0));
 177
 178     //
 179     // Means Allocate 4MB for GTTMADDR
 180     //
 181     MemBaseAddress = 0x0ffffffff;
 182
 183     Status = gDS->AllocateMemorySpace (
 184                     EfiGcdAllocateMaxAddressSearchBottomUp,
 185                     EfiGcdMemoryTypeMemoryMappedIo,
 186                     GTT_MEM_ALIGN,
 187                     GTTMMADR_SIZE_4MB,
 188                     &MemBaseAddress,
 189                     ImageHandle,
 190                     NULL
 191                     );
 192     ASSERT_EFI_ERROR (Status);
 193
 194     //
 195     // Program GT PM Settings if GTTMMADR allocation is Successful
 196     //
 197     GTTMMADR                          = (UINTN) MemBaseAddress;
 198
 199     LoGTBaseAddress                   = (UINT32) (MemBaseAddress & 0xFFFFFFFF);
 200     HiGTBaseAddress                   = (UINT32) RShiftU64 ((MemBaseAddress & 0xFFFFFFFF00000000), 32);
 201
 202     PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR), LoGTBaseAddress);
 203     PciWrite32 (PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR+4), HiGTBaseAddress);
 204
 205
 206     S3PciRead32(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_GTTMMADR));
 207
 208
 209     S3MmioRead32(IGD_R_GTTMMADR + 4);
 210
 211
 212     S3PciRead8(PCI_LIB_ADDRESS(0, IGD_DEV, 0, IGD_R_CMD));
 213
 214     //
 215     // Do POST GT PM Init Steps after VBIOS Initialization in DoPostPmInitCallBack
 216     //
 217     Status = gBS->CreateEvent (
 218                     EVT_NOTIFY_SIGNAL,
 219                     TPL_CALLBACK,
 220                     (EFI_EVENT_NOTIFY)PostPmInitCallBack,
 221                     NULL,
 222                     &mConOutEvent
 223                     );
 224
 225     ASSERT_EFI_ERROR (Status);
 226     if (EFI_ERROR (Status)) {
 227       return Status;
 228     }
 229
 230
 231     Status = gBS->RegisterProtocolNotify (
 232                     &gEfiGraphicsOutputProtocolGuid,
 233                     mConOutEvent,
 234                     &gConOutNotifyReg
 235                     );
 236
 237
 238
 239     MmioWrite64 (IGD_R_GTTMMADR, 0);
 240
 241     //
 242     // Free allocated resources
 243     //
 244     gDS->FreeMemorySpace (
 245            MemBaseAddress,
 246            GTTMMADR_SIZE_4MB
 247            );
 248
 249   }
 250
 251   return EFI_SUCCESS;
 252 }
 253
 254 /**
 255
 256   This is the standard EFI driver point that detects
 257   whether there is an ICH southbridge in the system
 258   and if so, initializes the chip.
 259
 260   @param  ImageHandle             Handle for the image of this driver
 261   @param  SystemTable             Pointer to the EFI System Table
 262
 263   @retval EFI_SUCCESS             The function completed successfully
 264
 265 **/
 266 EFI_STATUS
 267 EFIAPI
 268 VlvPlatformInitEntryPoint (
 269   IN EFI_HANDLE       ImageHandle,
 270   IN EFI_SYSTEM_TABLE *SystemTable
 271   )
 272 {
 273   EFI_STATUS                        Status;
 274
 275   Status = gBS->LocateProtocol (&gDxeVlvPlatformPolicyGuid, NULL, (void **)&DxePlatformSaPolicy);
 276   ASSERT_EFI_ERROR (Status);
 277
 278   //
 279   // GtPostInit Initialization
 280   //
 281   DEBUG ((EFI_D_ERROR, "Initializing GT PowerManagement and other GT POST related\n"));
 282   IgdPmHook (ImageHandle, DxePlatformSaPolicy);
 283
 284   //
 285   // IgdOpRegion Install Initialization
 286   //
 287   DEBUG ((EFI_D_ERROR, "Initializing IGD OpRegion\n"));
 288   IgdOpRegionInit ();
 289
 290   return EFI_SUCCESS;
 291 }
 292