Started working on an ArmEb package. GIC is ported. SEC is a start. Still missing...

[mirror_edk2.git] / ArmEbPkg / Sec / Cache.c

diff --git a/ArmEbPkg/Sec/Cache.c b/ArmEbPkg/Sec/Cache.c
new file mode 100644 (file)
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+++ b/ArmEbPkg/Sec/Cache.c
@@ -0,0 +1,79 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiPei.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/PrePiLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+// DDR attributes\r
+#define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
+#define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r
+\r
+// SoC registers. L3 interconnects\r
+#define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000\r
+#define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000\r
+#define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+// SoC registers. L4 interconnects\r
+#define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000\r
+#define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000\r
+#define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE\r
+\r
+VOID\r
+InitCache (\r
+  IN  UINT32  MemoryBase,\r
+  IN  UINT32  MemoryLength\r
+  )\r
+{\r
+  UINT32                        CacheAttributes;\r
+  ARM_MEMORY_REGION_DESCRIPTOR  MemoryTable[5];\r
+  VOID                          *TranslationTableBase;\r
+  UINTN                         TranslationTableSize;\r
+\r
+  if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r
+    CacheAttributes = DDR_ATTRIBUTES_CACHED;\r
+  } else {\r
+    CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r
+  }\r
+\r
+  // DDR\r
+  MemoryTable[0].PhysicalBase = MemoryBase;\r
+  MemoryTable[0].VirtualBase  = MemoryBase;\r
+  MemoryTable[0].Length       = MemoryLength;\r
+  MemoryTable[0].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
+\r
+  // SOC Registers. L3 interconnects\r
+  MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].VirtualBase  = SOC_REGISTERS_L3_PHYSICAL_BASE;\r
+  MemoryTable[1].Length       = SOC_REGISTERS_L3_PHYSICAL_LENGTH;\r
+  MemoryTable[1].Attributes   = SOC_REGISTERS_L3_ATTRIBUTES;\r
+  \r
+  // SOC Registers. L4 interconnects\r
+  MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].VirtualBase  = SOC_REGISTERS_L4_PHYSICAL_BASE;\r
+  MemoryTable[2].Length       = SOC_REGISTERS_L4_PHYSICAL_LENGTH;\r
+  MemoryTable[2].Attributes   = SOC_REGISTERS_L4_ATTRIBUTES;\r
+\r
+  // End of Table\r
+  MemoryTable[3].PhysicalBase = 0;\r
+  MemoryTable[3].VirtualBase  = 0;\r
+  MemoryTable[3].Length       = 0;\r
+  MemoryTable[3].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r
+  \r
+  ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize);\r
+  \r
+  BuildMemoryAllocationHob ((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
+}\r