# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
ArmLib|Include/Library/ArmLib.h\r
ArmMmuLib|Include/Library/ArmMmuLib.h\r
SemihostLib|Include/Library/Semihosting.h\r
- UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h\r
ArmGicArchLib|Include/Library/ArmGicArchLib.h\r
+ ArmMtlLib|ArmPlatformPkg/Include/Library/ArmMtlLib.h\r
+ ArmSvcLib|Include/Library/ArmSvcLib.h\r
+ OpteeLib|Include/Library/OpteeLib.h\r
+ StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h\r
\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
# Include/Guid/ArmMpCoreInfo.h\r
gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
+[Protocols.common]\r
+ ## Arm System Control and Management Interface(SCMI) Base protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h\r
+ gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h\r
+ gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }\r
+ gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }\r
+\r
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol\r
+ ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h\r
+ gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }\r
+\r
[Ppis]\r
## Include/Ppi/ArmMpCoreInfo.h\r
gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
\r
-[Protocols.common]\r
- gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
-\r
[PcdsFeatureFlag.common]\r
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
\r
# it has been configured by the CPU DXE\r
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032\r
\r
- # Define if the spin-table mechanism is used by the secondary cores when booting\r
- # Linux (instead of PSCI)\r
- gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033\r
-\r
# Define if the GICv3 controller should use the GICv2 legacy\r
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042\r
\r
+ # Whether to implement warm reboot for capsule update using a jump back to the\r
+ # PEI entry point with caches and interrupts disabled.\r
+ gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F\r
+\r
[PcdsFeatureFlag.ARM]\r
# Whether to map normal memory as non-shareable. FALSE is the safe choice, but\r
# TRUE may be appropriate to fix performance problems if you don't care about\r
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.\r
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024\r
\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
- # This PCD will free the unallocated buffers if their size reach this threshold.\r
- # We set the default value to 512MB.\r
- gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003\r
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004\r
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
\r
#\r
gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B\r
\r
- #\r
- # BdsLib\r
- #\r
- # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F\r
- # Maximum file size for TFTP servers that do not support 'tsize' extension\r
- gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000\r
-\r
#\r
# ARM Normal (or Non Secure) Firmware PCDs\r
#\r
# By default we do not do a transition to non-secure mode\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E\r
\r
- # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory\r
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020\r
-\r
- # If the fixed FDT address is not available, then it should be loaded below the kernel.\r
- # The recommendation from the Linux kernel is to have the FDT below 16KB.\r
- # (see the kernel doc: Documentation/arm/Booting)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 64bit aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026\r
-\r
# Non Secure Access Control Register\r
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality\r
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31\r
# Other modes include using SP0 or switching to Aarch32, but these are\r
# not currently supported.\r
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
- # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
- # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
- # (see the kernel doc: Documentation/arm64/booting.txt)\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
- # The FDT blob must be loaded at a 2MB aligned address.\r
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
\r
\r
#\r
[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r
\r
# System Memory (DRAM): These PCDs define the region of in-built system memory\r
- # Some platforms can get DRAM extensions, these additional regions will be declared\r
- # to UEFI by ArmPlatformLib\r
+ # Some platforms can get DRAM extensions, these additional regions may be\r
+ # declared to UEFI using separate resource descriptor HOBs\r
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
+ gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045\r
+ gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046\r
+\r
[PcdsFixedAtBuild.common, PcdsDynamic.common]\r
#\r
# ARM Architectural Timer\r
projects / mirror_edk2.git / blobdiff