-#------------------------------------------------------------------------------
-#
-# Use ARMv6 instruction to operate on a single stack
-#
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#------------------------------------------------------------------------------
-
-#include <Library/PcdLib.h>
-
-/*
-
-This is the stack constructed by the exception handler (low address to high address)
- # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
- Reg Offset
- === ======
- R0 0x00 # stmfd SP!,{R0-R12}
- R1 0x04
- R2 0x08
- R3 0x0c
- R4 0x10
- R5 0x14
- R6 0x18
- R7 0x1c
- R8 0x20
- R9 0x24
- R10 0x28
- R11 0x2c
- R12 0x30
- SP 0x34 # reserved via adding 0x20 (32) to the SP
- LR 0x38
- PC 0x3c
- CPSR 0x40
- DFSR 0x44
- DFAR 0x48
- IFSR 0x4c
- IFAR 0x50
-
- LR 0x54 # SVC Link register (we need to restore it)
-
- LR 0x58 # pushed by srsfd
- CPSR 0x5c
-
- */
-
-
-GCC_ASM_EXPORT(ExceptionHandlersStart)
-GCC_ASM_EXPORT(ExceptionHandlersEnd)
-GCC_ASM_EXPORT(CommonExceptionEntry)
-GCC_ASM_EXPORT(AsmCommonExceptionEntry)
-GCC_ASM_EXPORT(CommonCExceptionHandler)
-
-.text
-#if !defined(__APPLE__)
-.fpu neon @ makes vpush/vpop assemble
-#endif
-.align 5
-
-
-//
-// This code gets copied to the ARM vector table
-// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
-//
-ASM_PFX(ExceptionHandlersStart):
-
-ASM_PFX(Reset):
- b ASM_PFX(ResetEntry)
-
-ASM_PFX(UndefinedInstruction):
- b ASM_PFX(UndefinedInstructionEntry)
-
-ASM_PFX(SoftwareInterrupt):
- b ASM_PFX(SoftwareInterruptEntry)
-
-ASM_PFX(PrefetchAbort):
- b ASM_PFX(PrefetchAbortEntry)
-
-ASM_PFX(DataAbort):
- b ASM_PFX(DataAbortEntry)
-
-ASM_PFX(ReservedException):
- b ASM_PFX(ReservedExceptionEntry)
-
-ASM_PFX(Irq):
- b ASM_PFX(IrqEntry)
-
-ASM_PFX(Fiq):
- b ASM_PFX(FiqEntry)
-
-ASM_PFX(ResetEntry):
- srsdb #0x13! @ Store return state on SVC stack
- @ We are already in SVC mode
-
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#0 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(UndefinedInstructionEntry):
- sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#1 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(SoftwareInterruptEntry):
- sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
- srsdb #0x13! @ Store return state on SVC stack
- @ We are already in SVC mode
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#2 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(PrefetchAbortEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#3 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(DataAbortEntry):
- sub LR,LR,#8
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#4
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(ReservedExceptionEntry):
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#5
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(IrqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
-
- mov R0,#6 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-ASM_PFX(FiqEntry):
- sub LR,LR,#4
- srsdb #0x13! @ Store return state on SVC stack
- cps #0x13 @ Switch to SVC for common stack
- stmfd SP!,{LR} @ Store the link register for the current mode
- sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
- stmfd SP!,{R0-R12} @ Store the register state
- @ Since we have already switch to SVC R8_fiq - R12_fiq
- @ never get used or saved
- mov R0,#7 @ ExceptionType
- ldr R1,ASM_PFX(CommonExceptionEntry)
- bx R1
-
-//
-// This gets patched by the C code that patches in the vector table
-//
-ASM_PFX(CommonExceptionEntry):
- .word ASM_PFX(AsmCommonExceptionEntry)
-
-ASM_PFX(ExceptionHandlersEnd):
-
-//
-// This code runs from CpuDxe driver loaded address. It is patched into
-// CommonExceptionEntry.
-//
-ASM_PFX(AsmCommonExceptionEntry):
- mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
- str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
-
- mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
- str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
-
- mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
- str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
-
- mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
- str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
-
- ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
- str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
-
- add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
- and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
- cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
- cmpne R3, #0x10 @
- stmeqed R2, {lr}^ @ save unbanked lr
- @ else
- stmneed R2, {lr} @ save SVC lr
-
-
- ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
- @ Check to see if we have to adjust for Thumb entry
- sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
- cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb
- bhi NoAdjustNeeded
-
- tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
- addne R5, R5, #2 @ PC += 2@
- str R5,[SP,#0x58] @ Update LR value pused by srsfd
-
-NoAdjustNeeded:
-
- str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
-
- sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
- str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
-
- @ R0 is ExceptionType
- mov R1,SP @ R1 is SystemContext
-
-#if (FixedPcdGet32(PcdVFPEnabled))
- vpush {d0-d15} @ save vstm registers in case they are used in optimizations
-#endif
-
-/*
-VOID
-EFIAPI
-CommonCExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType, R0
- IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
- )
-
-*/
- blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler
-
-#if (FixedPcdGet32(PcdVFPEnabled))
- vpop {d0-d15}
-#endif
-
- ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
- mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
-
- ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
- mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
-
- ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
- str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
-
- ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
- str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
-
- add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
- add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
- and R1, R1, #0x1f @ Check to see if User or System Mode
- cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
- cmpne R1, #0x10 @
- ldmeqed R2, {lr}^ @ restore unbanked lr
- @ else
- ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
-
- ldmfd SP!,{R0-R12} @ Restore general purpose registers
- @ Exception handler can not change SP
-
- add SP,SP,#0x20 @ Clear out the remaining stack space
- ldmfd SP!,{LR} @ restore the link register for this context
- rfefd SP! @ return from exception via srsfd stack slot
-
+#------------------------------------------------------------------------------ \r
+#\r
+# Use ARMv6 instruction to operate on a single stack\r
+#\r
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+#\r
+# This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#include <Library/PcdLib.h>\r
+\r
+/*\r
+\r
+This is the stack constructed by the exception handler (low address to high address)\r
+ # R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM\r
+ Reg Offset\r
+ === ====== \r
+ R0 0x00 # stmfd SP!,{R0-R12}\r
+ R1 0x04\r
+ R2 0x08\r
+ R3 0x0c\r
+ R4 0x10\r
+ R5 0x14\r
+ R6 0x18\r
+ R7 0x1c\r
+ R8 0x20\r
+ R9 0x24\r
+ R10 0x28\r
+ R11 0x2c\r
+ R12 0x30\r
+ SP 0x34 # reserved via adding 0x20 (32) to the SP\r
+ LR 0x38\r
+ PC 0x3c\r
+ CPSR 0x40\r
+ DFSR 0x44\r
+ DFAR 0x48\r
+ IFSR 0x4c\r
+ IFAR 0x50\r
+ \r
+ LR 0x54 # SVC Link register (we need to restore it)\r
+ \r
+ LR 0x58 # pushed by srsfd \r
+ CPSR 0x5c \r
+\r
+ */\r
+ \r
+\r
+GCC_ASM_EXPORT(ExceptionHandlersStart)\r
+GCC_ASM_EXPORT(ExceptionHandlersEnd)\r
+GCC_ASM_EXPORT(CommonExceptionEntry)\r
+GCC_ASM_EXPORT(AsmCommonExceptionEntry)\r
+GCC_ASM_EXPORT(CommonCExceptionHandler)\r
+\r
+.text\r
+#if !defined(__APPLE__)\r
+.fpu neon @ makes vpush/vpop assemble\r
+#endif\r
+.align 5\r
+\r
+\r
+//\r
+// This code gets copied to the ARM vector table\r
+// ExceptionHandlersStart - ExceptionHandlersEnd gets copied\r
+//\r
+ASM_PFX(ExceptionHandlersStart):\r
+\r
+ASM_PFX(Reset):\r
+ b ASM_PFX(ResetEntry)\r
+\r
+ASM_PFX(UndefinedInstruction):\r
+ b ASM_PFX(UndefinedInstructionEntry)\r
+\r
+ASM_PFX(SoftwareInterrupt):\r
+ b ASM_PFX(SoftwareInterruptEntry)\r
+\r
+ASM_PFX(PrefetchAbort):\r
+ b ASM_PFX(PrefetchAbortEntry)\r
+\r
+ASM_PFX(DataAbort):\r
+ b ASM_PFX(DataAbortEntry)\r
+\r
+ASM_PFX(ReservedException):\r
+ b ASM_PFX(ReservedExceptionEntry)\r
+\r
+ASM_PFX(Irq):\r
+ b ASM_PFX(IrqEntry)\r
+\r
+ASM_PFX(Fiq):\r
+ b ASM_PFX(FiqEntry)\r
+\r
+ASM_PFX(ResetEntry):\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ @ We are already in SVC mode\r
+\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+ \r
+ mov R0,#0 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(UndefinedInstructionEntry):\r
+ sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#1 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(SoftwareInterruptEntry):\r
+ sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ @ We are already in SVC mode\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#2 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(PrefetchAbortEntry):\r
+ sub LR,LR,#4\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#3 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(DataAbortEntry):\r
+ sub LR,LR,#8\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#4\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(ReservedExceptionEntry):\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#5\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(IrqEntry):\r
+ sub LR,LR,#4\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+\r
+ mov R0,#6 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+ASM_PFX(FiqEntry):\r
+ sub LR,LR,#4\r
+ srsdb #0x13! @ Store return state on SVC stack\r
+ cps #0x13 @ Switch to SVC for common stack\r
+ stmfd SP!,{LR} @ Store the link register for the current mode\r
+ sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR\r
+ stmfd SP!,{R0-R12} @ Store the register state\r
+ @ Since we have already switch to SVC R8_fiq - R12_fiq\r
+ @ never get used or saved\r
+ mov R0,#7 @ ExceptionType\r
+ ldr R1,ASM_PFX(CommonExceptionEntry)\r
+ bx R1\r
+\r
+//\r
+// This gets patched by the C code that patches in the vector table\r
+//\r
+ASM_PFX(CommonExceptionEntry):\r
+ .word ASM_PFX(AsmCommonExceptionEntry)\r
+\r
+ASM_PFX(ExceptionHandlersEnd):\r
+\r
+//\r
+// This code runs from CpuDxe driver loaded address. It is patched into \r
+// CommonExceptionEntry.\r
+//\r
+ASM_PFX(AsmCommonExceptionEntry):\r
+ mrc p15, 0, R1, c6, c0, 2 @ Read IFAR\r
+ str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR \r
+ \r
+ mrc p15, 0, R1, c5, c0, 1 @ Read IFSR\r
+ str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR\r
+ \r
+ mrc p15, 0, R1, c6, c0, 0 @ Read DFAR\r
+ str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR\r
+ \r
+ mrc p15, 0, R1, c5, c0, 0 @ Read DFSR\r
+ str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR\r
+ \r
+ ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack \r
+ str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR\r
+\r
+ add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
+ and R3, R1, #0x1f @ Check CPSR to see if User or System Mode\r
+ cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))\r
+ cmpne R3, #0x10 @ \r
+ stmeqed R2, {lr}^ @ save unbanked lr\r
+ @ else \r
+ stmneed R2, {lr} @ save SVC lr\r
+\r
+\r
+ ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd \r
+ @ Check to see if we have to adjust for Thumb entry\r
+ sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {\r
+ cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb \r
+ bhi NoAdjustNeeded\r
+ \r
+ tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry \r
+ addne R5, R5, #2 @ PC += 2@\r
+ str R5,[SP,#0x58] @ Update LR value pused by srsfd \r
+ \r
+NoAdjustNeeded:\r
+\r
+ str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC\r
+ \r
+ sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack \r
+ str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP\r
+ \r
+ @ R0 is ExceptionType \r
+ mov R1,SP @ R1 is SystemContext \r
+\r
+#if (FixedPcdGet32(PcdVFPEnabled))\r
+ vpush {d0-d15} @ save vstm registers in case they are used in optimizations\r
+#endif\r
+\r
+/* \r
+VOID\r
+EFIAPI\r
+CommonCExceptionHandler (\r
+ IN EFI_EXCEPTION_TYPE ExceptionType, R0\r
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext R1\r
+ )\r
+\r
+*/ \r
+ blx ASM_PFX(CommonCExceptionHandler) @ Call exception handler\r
+\r
+#if (FixedPcdGet32(PcdVFPEnabled))\r
+ vpop {d0-d15} \r
+#endif\r
+\r
+ ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR\r
+ mcr p15, 0, R1, c5, c0, 1 @ Write IFSR\r
+\r
+ ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR\r
+ mcr p15, 0, R1, c5, c0, 0 @ Write DFSR\r
+ \r
+ ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC\r
+ str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored \r
+\r
+ ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR\r
+ str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored \r
+ \r
+ add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry\r
+ add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR\r
+ and R1, R1, #0x1f @ Check to see if User or System Mode\r
+ cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))\r
+ cmpne R1, #0x10 @ \r
+ ldmeqed R2, {lr}^ @ restore unbanked lr\r
+ @ else\r
+ ldmneed R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}\r
+ \r
+ ldmfd SP!,{R0-R12} @ Restore general purpose registers\r
+ @ Exception handler can not change SP\r
+ \r
+ add SP,SP,#0x20 @ Clear out the remaining stack space\r
+ ldmfd SP!,{LR} @ restore the link register for this context\r
+ rfefd SP! @ return from exception via srsfd stack slot\r
+ \r
projects / mirror_edk2.git / blobdiff