\r
#include <Guid/IdleLoopEvent.h>\r
\r
-BOOLEAN mIsFlushingGCD;\r
+BOOLEAN mIsFlushingGCD;\r
\r
/**\r
This function flushes the range of addresses from Start to Start+Length\r
EFI_STATUS\r
EFIAPI\r
CpuFlushCpuDataCache (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_PHYSICAL_ADDRESS Start,\r
- IN UINT64 Length,\r
- IN EFI_CPU_FLUSH_TYPE FlushType\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_PHYSICAL_ADDRESS Start,\r
+ IN UINT64 Length,\r
+ IN EFI_CPU_FLUSH_TYPE FlushType\r
)\r
{\r
-\r
switch (FlushType) {\r
case EfiCpuFlushTypeWriteBack:\r
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function enables interrupt processing by the processor.\r
\r
EFI_STATUS\r
EFIAPI\r
CpuEnableInterrupt (\r
- IN EFI_CPU_ARCH_PROTOCOL *This\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
)\r
{\r
ArmEnableInterrupts ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function disables interrupt processing by the processor.\r
\r
EFI_STATUS\r
EFIAPI\r
CpuDisableInterrupt (\r
- IN EFI_CPU_ARCH_PROTOCOL *This\r
+ IN EFI_CPU_ARCH_PROTOCOL *This\r
)\r
{\r
ArmDisableInterrupts ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function retrieves the processor's current interrupt state a returns it in\r
State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
EFI_STATUS\r
EFIAPI\r
CpuGetInterruptState (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- OUT BOOLEAN *State\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ OUT BOOLEAN *State\r
)\r
{\r
if (State == NULL) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- *State = ArmGetInterruptState();\r
+ *State = ArmGetInterruptState ();\r
return EFI_SUCCESS;\r
}\r
\r
-\r
/**\r
This function generates an INIT on the processor. If this function succeeds, then the\r
processor will be reset, and control will not be returned to the caller. If InitType is\r
EFI_STATUS\r
EFIAPI\r
CpuInit (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_CPU_INIT_TYPE InitType\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_CPU_INIT_TYPE InitType\r
)\r
{\r
return EFI_UNSUPPORTED;\r
EFI_STATUS\r
EFIAPI\r
CpuRegisterInterruptHandler (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN EFI_EXCEPTION_TYPE InterruptType,\r
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN EFI_EXCEPTION_TYPE InterruptType,\r
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
)\r
{\r
return RegisterInterruptHandler (InterruptType, InterruptHandler);\r
EFI_STATUS\r
EFIAPI\r
CpuGetTimerValue (\r
- IN EFI_CPU_ARCH_PROTOCOL *This,\r
- IN UINT32 TimerIndex,\r
- OUT UINT64 *TimerValue,\r
- OUT UINT64 *TimerPeriod OPTIONAL\r
+ IN EFI_CPU_ARCH_PROTOCOL *This,\r
+ IN UINT32 TimerIndex,\r
+ OUT UINT64 *TimerValue,\r
+ OUT UINT64 *TimerPeriod OPTIONAL\r
)\r
{\r
return EFI_UNSUPPORTED;\r
VOID\r
EFIAPI\r
IdleLoopEventCallback (\r
- IN EFI_EVENT Event,\r
- IN VOID *Context\r
+ IN EFI_EVENT Event,\r
+ IN VOID *Context\r
)\r
{\r
CpuSleep ();\r
//\r
// Globals used to initialize the protocol\r
//\r
-EFI_HANDLE mCpuHandle = NULL;\r
-EFI_CPU_ARCH_PROTOCOL mCpu = {\r
+EFI_HANDLE mCpuHandle = NULL;\r
+EFI_CPU_ARCH_PROTOCOL mCpu = {\r
CpuFlushCpuDataCache,\r
CpuEnableInterrupt,\r
CpuDisableInterrupt,\r
STATIC\r
VOID\r
InitializeDma (\r
- IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol\r
)\r
{\r
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
\r
EFI_STATUS\r
CpuDxeInitialize (\r
- IN EFI_HANDLE ImageHandle,\r
- IN EFI_SYSTEM_TABLE *SystemTable\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
EFI_STATUS Status;\r
- EFI_EVENT IdleLoopEvent;\r
+ EFI_EVENT IdleLoopEvent;\r
\r
InitializeExceptions (&mCpu);\r
\r
InitializeDma (&mCpu);\r
\r
Status = gBS->InstallMultipleProtocolInterfaces (\r
- &mCpuHandle,\r
- &gEfiCpuArchProtocolGuid, &mCpu,\r
- NULL\r
- );\r
+ &mCpuHandle,\r
+ &gEfiCpuArchProtocolGuid,\r
+ &mCpu,\r
+ NULL\r
+ );\r
\r
//\r
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()\r
\r
// If the platform is a MPCore system then install the Configuration Table describing the\r
// secondary core states\r
- if (ArmIsMpCore()) {\r
- PublishArmProcessorTable();\r
+ if (ArmIsMpCore ()) {\r
+ PublishArmProcessorTable ();\r
}\r
\r
//\r