ArmPkg/PL35xSmc: Split the SMC initialization in multiple Chip Select initialization...

[mirror_edk2.git] / ArmPkg / Drivers / PL35xSmc / InitializeSMC.S

diff --git a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
index b3b597a50c60eb489317677c7cc387c8b69408eb..108cd6ae65bf4fcd121e887c81e9c82a1346cac0 100644 (file)
--- a/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
+++ b/ArmPkg/Drivers/PL35xSmc/InitializeSMC.S
@@ -14,7 +14,7 @@
 #include <AsmMacroIoLib.h>\r
 #include <Library/PcdLib.h>\r
 #include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
+#include <Drivers/PL354Smc.h>\r
 \r
 #Start of the code section\r
 .text\r
@@ -22,13 +22,12 @@
 #Maintain 8 byte alignment\r
 .align 3\r
 \r
-#Export Initialize SMC symbol\r
-GCC_ASM_EXPORT(InitializeSMC)\r
 \r
-# Static memory configuation definitions for SMC\r
-.set        SmcDirectCmd,              0x10\r
-.set        SmcSetCycles,              0x14\r
-.set        SmcSetOpMode,              0x18\r
+GCC_ASM_EXPORT(SMCInitializeNOR)\r
+GCC_ASM_EXPORT(SMCInitializeSRAM)\r
+GCC_ASM_EXPORT(SMCInitializePeripherals)\r
+GCC_ASM_EXPORT(SMCInitializeVRAM)\r
+\r
 \r
 # CS0  CS0-Interf0     NOR1 flash on the motherboard\r
 # CS1  CS1-Interf0     Reserved for the motherboard\r
@@ -39,125 +38,134 @@ GCC_ASM_EXPORT(InitializeSMC)
 # CS6  CS2-Interf1     memory-mapped peripherals\r
 # CS7  CS3-Interf1     system memory-mapped peripherals on the motherboard.\r
 \r
-# IN r1 SmcBase\r
-# IN r2 VideoSRamBase\r
-# NOTE: This code is been called before any stack has been setup. It means some registers\r
-#       could be overwritten (case of 'r0')\r
-\r
-\r
-ASM_PFX(InitializeSMC):\r
+// IN r1 SmcBase\r
+// IN r2 ChipSelect\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+//       could be overwritten (case of 'r0')\r
+ASM_PFX(SMCInitializeNOR):\r
 #\r
 # Setup NOR1 (CS0-Interface0)\r
 #\r
 \r
-  #Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+  # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
      #Read cycle timeout = 0xA (0:3)\r
      #Write cycle timeout = 0x3(7:4)\r
      #OE Assertion Delay = 0x9(11:8)\r
      #WE Assertion delay = 0x3(15:12)\r
      #Page cycle timeout = 0x2(19:16)  \r
   LoadConstantToReg (0x0002393A,r0)       @ldr     r0, = 0x0002393A\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
   \r
-  #Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+  # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
      # 0x00000002 = MemoryWidth: 32bit\r
      # 0x00000028 = ReadMemoryBurstLength:continuous\r
      # 0x00000280 = WriteMemoryBurstLength:continuous\r
      # 0x00000800 = Set Address Valid\r
   LoadConstantToReg (0x00000AAA,r0)       @ldr     r0, = 0x00000AAA\r
-  str     r0, [r1, #SmcSetOpMode]    \r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
 \r
- #Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
      # 0x00000000 = ChipSelect0-Interface 0\r
      # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x00400000,r0)       @ldr     r0, = 0x00400000\r
-  str     r0, [r1, #SmcDirectCmd]                              \r
-  \r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
   \r
+  bx lr\r
+\r
+ASM_PFX(SMCInitializeSRAM):\r
 #\r
 # Setup SRAM (CS2-Interface0)\r
 #\r
   LoadConstantToReg (0x00027158,r0)       @ldr     r0, = 0x00027158\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
 \r
   # 0x00000002 = MemoryWidth: 32bit\r
   # 0x00000800 = Set Address Valid\r
   LoadConstantToReg (0x00000802,r0)       @ldr     r0, = 0x00000802\r
-  str     r0, [r1, #SmcSetOpMode]\r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
   \r
   # 0x01000000 = ChipSelect2-Interface 0\r
   # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x01400000,r0)       @ldr     r0, = 0x01400000\r
-  str     r0, [r1, #SmcDirectCmd]\r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+  bx    lr\r
 \r
+ASM_PFX(SMCInitializePeripherals):\r
 #\r
 # USB/Eth/VRAM (CS3-Interface0)\r
 #\r
   LoadConstantToReg (0x000CD2AA,r0)      @ldr     r0, = 0x000CD2AA\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
   # 0x00000002 = MemoryWidth: 32bit\r
   # 0x00000004 = Memory reads are synchronous\r
   # 0x00000040 = Memory writes are synchronous\r
   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
-  str     r0, [r1, #SmcSetOpMode]  \r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
         \r
   # 0x01800000 = ChipSelect3-Interface 0\r
   # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x01C00000,r0)      @ldr     r0, = 0x01C00000\r
-  str     r0, [r1, #SmcDirectCmd]  \r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
 \r
 #\r
 # Setup NOR3 (CS0-Interface1)\r
 #\r
   LoadConstantToReg (0x0002393A,r0)      @ldr     r0, = 0x0002393A\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
   # 0x00000002 = MemoryWidth: 32bit\r
   # 0x00000028 = ReadMemoryBurstLength:continuous\r
   # 0x00000280 = WriteMemoryBurstLength:continuous\r
   # 0x00000800 = Set Address Valid\r
   LoadConstantToReg (0x00000AAA,r0)      @ldr     r0, = 0x00000AAA\r
-  str     r0, [r1, #SmcSetOpMode]  \r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
         \r
   # 0x02000000 = ChipSelect0-Interface 1\r
   # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x02400000,r0)      @ldr     r0, = 0x02400000\r
-  str     r0, [r1, #SmcDirectCmd]  \r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
  \r
 #\r
 # Setup Peripherals (CS3-Interface1)\r
 #\r
   LoadConstantToReg (0x00025156,r0)      @ldr     r0, = 0x00025156\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
   # 0x00000002 = MemoryWidth: 32bit\r
   # 0x00000004 = Memory reads are synchronous\r
   # 0x00000040 = Memory writes are synchronous\r
   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
-  str     r0, [r1, #SmcSetOpMode]  \r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
         \r
   # 0x03800000 = ChipSelect3-Interface 1\r
   # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x03C00000,r0)      @ldr     r0, = 0x03C00000\r
-  str     r0, [r1, #SmcDirectCmd] \r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+  bx    lr\r
 \r
+// IN r1 SmcBase\r
+// IN r2 VideoSRamBase\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+//       could be overwritten (case of 'r0')\r
+ASM_PFX(SMCInitializeVRAM):\r
 #\r
 # Setup VRAM (CS1-Interface0)\r
 #\r
   LoadConstantToReg (0x00049249,r0)      @ldr     r0, =  0x00049249\r
-  str     r0, [r1, #SmcSetCycles]\r
+  str     r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
  \r
   # 0x00000002 = MemoryWidth: 32bit\r
   # 0x00000004 = Memory reads are synchronous\r
   # 0x00000040 = Memory writes are synchronous\r
   LoadConstantToReg (0x00000046,r0)      @ldr     r0, = 0x00000046\r
-  str     r0, [r1, #SmcSetOpMode]  \r
+  str     r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
         \r
   # 0x00800000 = ChipSelect1-Interface 0\r
   # 0x00400000 = CmdTypes: UpdateRegs\r
   LoadConstantToReg (0x00C00000,r0)      @ldr     r0, = 0x00C00000\r
-  str     r0, [r1, #SmcDirectCmd]  \r
+  str     r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
   \r
 #\r
 # Page mode setup for VRAM\r