ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers when...

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicDxe.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
index ce96831a427d3bd115dd06904848a4d6d5539c0c..111ce144385ba0dfb88cf16037a1b40ce7c00947 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
@@ -378,12 +378,12 @@ InterruptDxeInitialize (
   CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
 \r
   // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
-  // cannot be 0.\r
-  ASSERT (CpuTarget != 0);\r
-\r
-  // The 8 first Interrupt Processor Targets Registers are read-only\r
-  for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
-    MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+  // is 0 when we run on a uniprocessor platform.\r
+  if (CpuTarget != 0) {\r
+    // The 8 first Interrupt Processor Targets Registers are read-only\r
+    for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
+      MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
+    }\r
   }\r
 \r
   // Set binary point reg to 0x7 (no preemption)\r