);\r
}\r
\r
- // Configure interrupts for Primary Cpu\r
- CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));\r
- CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);\r
- for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {\r
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);\r
+ //\r
+ // Targets the interrupts to the Primary Cpu\r
+ //\r
+\r
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading\r
+ // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each\r
+ // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.\r
+ // More Info in the GIC Specification about "Interrupt Processor Targets Registers"\r
+ //\r
+ // Read the first Interrupt Processor Targets Register (that corresponds to the 4\r
+ // first SGIs)\r
+ CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);\r
+\r
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value\r
+ // cannot be 0.\r
+ ASSERT (CpuTarget != 0);\r
+\r
+ // The 8 first Interrupt Processor Targets Registers are read-only\r
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {\r
+ MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);\r
}\r
\r
// Set binary point reg to 0x7 (no preemption)\r