PL390GicEnableInterruptInterface (\r
IN INTN GicInterruptInterfaceBase\r
)\r
-{ \r
- /*\r
- * Enable the CPU interface in Non-Secure world\r
- * Note: The ICCICR register is banked when Security extensions are implemented \r
- */\r
+{ \r
+ /*\r
+ * Enable the CPU interface in Non-Secure world\r
+ * Note: The ICCICR register is banked when Security extensions are implemented \r
+ */\r
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
}\r
\r
IN INTN CPUTargetList\r
)\r
{\r
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+ MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
}\r
\r
UINT32\r
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
+ //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
return 1;\r
} else {\r
return 0;\r
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
- //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
+ //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
return 1;\r
} else {\r
return 0;\r