//Check if there are any pending interrupts\r
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))\r
{\r
-\s\s //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-\s\s UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+ //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
+ UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
-\s\s //Write to End of interrupt signal\r
-\s\s MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ //Write to End of interrupt signal\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
}\r
\r
// Ensure all GIC interrupts are Non-Secure\r
IN INTN GicInterruptInterfaceBase\r
)\r
{\r
-\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r
\r
-\s\s/*\r
-\s\s * Enable CPU interface in Secure world\r
+ /*\r
+ * Enable CPU interface in Secure world\r
* Enable CPU inteface in Non-secure World\r
-\s\s * Signal Secure Interrupts to CPU using FIQ line *\r
-\s\s */\r
+ * Signal Secure Interrupts to CPU using FIQ line *\r
+ */\r
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
- \s\s\s\sGIC_ICCICR_ENABLE_SECURE(1) |\r
- \s\s\s\sGIC_ICCICR_ENABLE_NS(1) |\r
- \s\s\s\sGIC_ICCICR_ACK_CTL(0) |\r
- \s\s\s\sGIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
- \s\s\s\sGIC_ICCICR_USE_SBPR(0));\r
+ GIC_ICCICR_ENABLE_SECURE(1) |\r
+ GIC_ICCICR_ENABLE_NS(1) |\r
+ GIC_ICCICR_ACK_CTL(0) |\r
+ GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
+ GIC_ICCICR_USE_SBPR(0));\r
}\r
\r
VOID\r
IN INTN CPUTargetList\r
)\r
{\r
-\s\sMmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+ MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
}\r
\r
UINT32\r
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
-\s\sif (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
-\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
+ //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
return 1;\r
} else {\r
return 0;\r
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
\r
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
-\s\sif((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
-\s\s //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
-\s\s\s\sMmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
+ //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
return 1;\r
} else {\r
return 0;\r