ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
}\r
\r
+VOID\r
+EFIAPI\r
+ArmGicDisableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ )\r
+{\r
+ UINT32 ControlValue;\r
+\r
+ // Disable CPU interface in Secure world and Non-secure World\r
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));\r
+}\r
+\r
VOID\r
EFIAPI\r
ArmGicEnableDistributor (\r