// Set priority Mask so that no interrupts get through to CPU\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
\r
- // Check if there are any pending interrupts\r
- //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
- while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
- // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
\r
- // Write to End of interrupt signal\r
+ // Only try to clear valid interrupts. Ignore spurious interrupts.\r
+ while ((InterruptId & 0x3FF) < ArmGicGetMaxNumInterrupts (GicDistributorBase)) {\r
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+\r
+ // Next\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
}\r
\r
// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r