ArmPkg: Fix coding style to follow EDK2 coding convention

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 156e0601e8770e9ef08a37fc3d76f6ddf47e18fd..bf4c010b7043a57ea71b67d3c79933e53f976e6a 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -12,6 +12,7 @@
 *\r
 **/\r
 \r
+#include <Uefi.h>\r
 #include <Library/IoLib.h>\r
 #include <Drivers/PL390Gic.h>\r
 \r
@@ -26,28 +27,27 @@ PL390GicSetupNonSecure (
   IN  INTN          GicInterruptInterfaceBase\r
   )\r
 {\r
-   UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r
+  UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r
 \r
-   //Set priority Mask so that no interrupts get through to CPU\r
-   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r
+  // Set priority Mask so that no interrupts get through to CPU\r
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r
 \r
-   //Check if there are any pending interrupts\r
-   while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF))\r
-   {\r
-     //Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
-     UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+  // Check if there are any pending interrupts\r
+  while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {\r
+    // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
+    UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
 \r
-     //Write to End of interrupt signal\r
-     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-   }\r
+    // Write to End of interrupt signal\r
+    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+  }\r
 \r
   // Ensure all GIC interrupts are Non-Secure\r
-   MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
-   MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
-   MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+  MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff);     // IRQs  0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
+  MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
+  MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
 \r
   // Ensure all interrupts can get through the priority mask\r
-   MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r
 }\r
 \r
 VOID\r
@@ -63,12 +63,12 @@ PL390GicEnableInterruptInterface (
      * Enable CPU inteface in Non-secure World\r
    * Signal Secure Interrupts to CPU using FIQ line *\r
    */\r
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
-        GIC_ICCICR_ENABLE_SECURE(1) |\r
-        GIC_ICCICR_ENABLE_NS(1) |\r
-        GIC_ICCICR_ACK_CTL(0) |\r
-        GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
-        GIC_ICCICR_USE_SBPR(0));\r
+  MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
+      GIC_ICCICR_ENABLE_SECURE(1) |\r
+      GIC_ICCICR_ENABLE_NS(1) |\r
+      GIC_ICCICR_ACK_CTL(0) |\r
+      GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
+      GIC_ICCICR_USE_SBPR(0));\r
 }\r
 \r
 VOID\r
@@ -77,7 +77,7 @@ PL390GicEnableDistributor (
   IN  INTN          GicDistributorBase\r
   )\r
 {\r
-    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1);               // turn on the GIC distributor\r
+  MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1);               // turn on the GIC distributor\r
 }\r
 \r
 VOID\r
@@ -98,18 +98,18 @@ PL390GicAcknowledgeSgiFrom (
   IN  INTN          CoreId\r
   )\r
 {\r
-    INTN            InterruptId;\r
+  INTN            InterruptId;\r
 \r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
 \r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
   if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
+    return 1;\r
+  } else {\r
+    return 0;\r
+  }\r
 }\r
 \r
 UINT32\r
@@ -120,16 +120,16 @@ PL390GicAcknowledgeSgi2From (
   IN  INTN          SgiId\r
   )\r
 {\r
-    INTN            InterruptId;\r
+  INTN            InterruptId;\r
 \r
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
 \r
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
   if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
     MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
-        return 1;\r
-    } else {\r
-        return 0;\r
-    }\r
+    return 1;\r
+  } else {\r
+    return 0;\r
+  }\r
 }\r