ArmPkg: Replaced gArmTokenSpaceGuid.PcdGicNumInterrupts by ArmGicGetMaxNumInterrupts()

[mirror_edk2.git] / ArmPkg / Drivers / PL390Gic / PL390GicSec.c

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
index 12f9e3e3fcacdcc12659173a5a59a88a735bafa8..c137c95f20587951a850ce280b20ead406ca4b08 100644 (file)
--- a/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicSec.c
@@ -52,7 +52,7 @@ ArmGicSetupNonSecure (
   // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).\r
   if (IS_PRIMARY_CORE(MpId)) {\r
     // Ensure all GIC interrupts are Non-Secure\r
-    for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {\r
+    for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {\r
       MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);\r
     }\r
   } else {\r
@@ -80,7 +80,7 @@ ArmGicSetSecureInterrupts (
   UINT32 InterruptStatus;\r
 \r
   // We must not have more interrupts defined by the mask than the number of available interrupts\r
-  ASSERT(GicSecureInterruptMaskSize <= (PcdGet32(PcdGicNumInterrupts) / 32));\r
+  ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));\r
 \r
   // Set all the interrupts defined by the mask as Secure\r
   for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {\r