#ifndef ARM_MP_CORE_INFO_GUID_H_\r
#define ARM_MP_CORE_INFO_GUID_H_\r
\r
-#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
-#define SCU_CONFIG_REG_OFFSET 0x04\r
-#define MPIDR_U_BIT_MASK 0x40000000\r
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
+#define SCU_CONFIG_REG_OFFSET 0x04\r
+#define MPIDR_U_BIT_MASK 0x40000000\r
\r
typedef struct {\r
- UINT32 ClusterId;\r
- UINT32 CoreId;\r
+ UINT32 ClusterId;\r
+ UINT32 CoreId;\r
\r
// MP Core Mailbox\r
- EFI_PHYSICAL_ADDRESS MailboxSetAddress;\r
- EFI_PHYSICAL_ADDRESS MailboxGetAddress;\r
- EFI_PHYSICAL_ADDRESS MailboxClearAddress;\r
- UINT64 MailboxClearValue;\r
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;\r
+ UINT64 MailboxClearValue;\r
} ARM_CORE_INFO;\r
\r
-typedef struct{\r
- UINT64 Signature;\r
- UINT32 Length;\r
- UINT32 Revision;\r
- UINT64 OemId;\r
- UINT64 OemTableId;\r
- UINTN OemRevision;\r
- UINTN CreatorId;\r
- UINTN CreatorRevision;\r
- EFI_GUID Identifier;\r
- UINTN DataLen;\r
+typedef struct {\r
+ UINT64 Signature;\r
+ UINT32 Length;\r
+ UINT32 Revision;\r
+ UINT64 OemId;\r
+ UINT64 OemTableId;\r
+ UINTN OemRevision;\r
+ UINTN CreatorId;\r
+ UINTN CreatorRevision;\r
+ EFI_GUID Identifier;\r
+ UINTN DataLen;\r
} ARM_PROCESSOR_TABLE_HEADER;\r
\r
typedef struct {\r
- ARM_PROCESSOR_TABLE_HEADER Header;\r
- UINTN NumberOfEntries;\r
- ARM_CORE_INFO *ArmCpus;\r
+ ARM_PROCESSOR_TABLE_HEADER Header;\r
+ UINTN NumberOfEntries;\r
+ ARM_CORE_INFO *ArmCpus;\r
} ARM_PROCESSOR_TABLE;\r
\r
-\r
#define ARM_MP_CORE_INFO_GUID \\r
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
\r
-#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')\r
-#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')\r
-#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001\r
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5\r
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001\r
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')\r
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001\r
\r
-extern EFI_GUID gArmMpCoreInfoGuid;\r
+extern EFI_GUID gArmMpCoreInfoGuid;\r
\r
#endif /* ARM_MP_CORE_INFO_GUID_H_ */\r