ArmPkg: Apply uncrustify changes

[mirror_edk2.git] / ArmPkg / Include / IndustryStandard / ArmCache.h

diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h
index f9de46b5bffd9b1a91c1dde55869417ec3d5bbc3..27a91fcda2d59a1365bf47be2bcc6ee2030e160d 100644 (file)
--- a/ArmPkg/Include/IndustryStandard/ArmCache.h
+++ b/ArmPkg/Include/IndustryStandard/ArmCache.h
@@ -13,22 +13,21 @@
 \r
 // The ARM Architecture Reference Manual for ARMv8-A defines up\r
 // to 7 levels of cache, L1 through L7.\r
-#define MAX_ARM_CACHE_LEVEL   7\r
+#define MAX_ARM_CACHE_LEVEL  7\r
 \r
 /// Defines the structure of the CSSELR (Cache Size Selection) register\r
 typedef union {\r
   struct {\r
-    UINT32    InD       :1;  ///< Instruction not Data bit\r
-    UINT32    Level     :3;  ///< Cache level (zero based)\r
-    UINT32    TnD       :1;  ///< Allocation not Data bit\r
-    UINT32    Reserved  :27; ///< Reserved, RES0\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
+    UINT32    InD      : 1;  ///< Instruction not Data bit\r
+    UINT32    Level    : 3;  ///< Cache level (zero based)\r
+    UINT32    TnD      : 1;  ///< Allocation not Data bit\r
+    UINT32    Reserved : 27; ///< Reserved, RES0\r
+  } Bits;         ///< Bitfield definition of the register\r
+  UINT32    Data; ///< The entire 32-bit value\r
 } CSSELR_DATA;\r
 \r
 /// The cache type values for the InD field of the CSSELR register\r
-typedef enum\r
-{\r
+typedef enum {\r
   /// Select the data or unified cache\r
   CsselrCacheTypeDataOrUnified = 0,\r
   /// Select the instruction cache\r
@@ -39,35 +38,35 @@ typedef enum
 /// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
 typedef union {\r
   struct {\r
-    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
-    UINT64    Associativity      :10; ///< Associativity - 1\r
-    UINT64    NumSets            :15; ///< Number of sets in the cache -1\r
-    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN\r
-    UINT64    Reserved           :32; ///< Reserved, RES0\r
+    UINT64    LineSize      : 3;      ///< Line size (Log2(Num bytes in cache) - 4)\r
+    UINT64    Associativity : 10;     ///< Associativity - 1\r
+    UINT64    NumSets       : 15;     ///< Number of sets in the cache -1\r
+    UINT64    Unknown       : 4;      ///< Reserved, UNKNOWN\r
+    UINT64    Reserved      : 32;     ///< Reserved, RES0\r
   } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
   struct {\r
-    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
-    UINT64    Associativity      :21; ///< Associativity - 1\r
-    UINT64    Reserved1          :8;  ///< Reserved, RES0\r
-    UINT64    NumSets            :24; ///< Number of sets in the cache -1\r
-    UINT64    Reserved2          :8;  ///< Reserved, RES0\r
+    UINT64    LineSize      : 3;      ///< Line size (Log2(Num bytes in cache) - 4)\r
+    UINT64    Associativity : 21;     ///< Associativity - 1\r
+    UINT64    Reserved1     : 8;      ///< Reserved, RES0\r
+    UINT64    NumSets       : 24;     ///< Number of sets in the cache -1\r
+    UINT64    Reserved2     : 8;      ///< Reserved, RES0\r
   } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
   struct {\r
-    UINT64    LineSize           : 3;\r
-    UINT64    Associativity      : 21;\r
-    UINT64    Reserved           : 8;\r
-    UINT64    Unallocated        : 32;\r
+    UINT64    LineSize      : 3;\r
+    UINT64    Associativity : 21;\r
+    UINT64    Reserved      : 8;\r
+    UINT64    Unallocated   : 32;\r
   } BitsCcidxAA32;\r
-  UINT64 Data; ///< The entire 64-bit value\r
+  UINT64    Data; ///< The entire 64-bit value\r
 } CCSIDR_DATA;\r
 \r
 /// Defines the structure of the AARCH32 CCSIDR2 register.\r
 typedef union {\r
   struct {\r
-    UINT32 NumSets               :24; ///< Number of sets in the cache - 1\r
-    UINT32 Reserved              :8;  ///< Reserved, RES0\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
+    UINT32    NumSets  : 24;          ///< Number of sets in the cache - 1\r
+    UINT32    Reserved : 8;           ///< Reserved, RES0\r
+  } Bits;         ///< Bitfield definition of the register\r
+  UINT32    Data; ///< The entire 32-bit value\r
 } CCSIDR2_DATA;\r
 \r
 /** Defines the structure of the CLIDR (Cache Level ID) register.\r
@@ -77,19 +76,19 @@ typedef union {
 **/\r
 typedef union {\r
   struct {\r
-    UINT32    Ctype1   : 3; ///< Level 1 cache type\r
-    UINT32    Ctype2   : 3; ///< Level 2 cache type\r
-    UINT32    Ctype3   : 3; ///< Level 3 cache type\r
-    UINT32    Ctype4   : 3; ///< Level 4 cache type\r
-    UINT32    Ctype5   : 3; ///< Level 5 cache type\r
-    UINT32    Ctype6   : 3; ///< Level 6 cache type\r
-    UINT32    Ctype7   : 3; ///< Level 7 cache type\r
-    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable\r
-    UINT32    LoC      : 3; ///< Level of Coherency\r
-    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor\r
-    UINT32    Icb      : 3; ///< Inner Cache Boundary\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
+    UINT32    Ctype1 : 3;   ///< Level 1 cache type\r
+    UINT32    Ctype2 : 3;   ///< Level 2 cache type\r
+    UINT32    Ctype3 : 3;   ///< Level 3 cache type\r
+    UINT32    Ctype4 : 3;   ///< Level 4 cache type\r
+    UINT32    Ctype5 : 3;   ///< Level 5 cache type\r
+    UINT32    Ctype6 : 3;   ///< Level 6 cache type\r
+    UINT32    Ctype7 : 3;   ///< Level 7 cache type\r
+    UINT32    LoUIS  : 3;   ///< Level of Unification Inner Shareable\r
+    UINT32    LoC    : 3;   ///< Level of Coherency\r
+    UINT32    LoUU   : 3;   ///< Level of Unification Uniprocessor\r
+    UINT32    Icb    : 3;   ///< Inner Cache Boundary\r
+  } Bits;         ///< Bitfield definition of the register\r
+  UINT32    Data; ///< The entire 32-bit value\r
 } CLIDR_DATA;\r
 \r
 /// The cache types reported in the CLIDR register.\r
@@ -107,6 +106,6 @@ typedef enum {
   ClidrCacheTypeMax\r
 } CLIDR_CACHE_TYPE;\r
 \r
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
+#define CLIDR_GET_CACHE_TYPE(x, level)  ((x >> (3 * (level))) & 0b111)\r
 \r
 #endif /* ARM_CACHE_H_ */\r