* privileged operations on its behalf.\r
*/\r
#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065\r
#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061\r
#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064\r
#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065\r
\r
+/* Generic IDs when using AArch32 or AArch64 execution state */\r
+#ifdef MDE_CPU_AARCH64\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64\r
+#endif\r
+#ifdef MDE_CPU_ARM\r
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32\r
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32\r
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32\r
+#endif\r
+\r
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3\r
#define SET_MEM_ATTR_DATA_PERM_SHIFT 0\r
#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0\r