-/** @file
-
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __ARM_LIB__
-#define __ARM_LIB__
-
-#include <Uefi/UefiBaseType.h>
-
-#ifdef ARM_CPU_ARMv6
-#include <Chipset/ARM1176JZ-S.h>
-#else
-#include <Chipset/ArmV7.h>
-#endif
-
-typedef enum {
- ARM_CACHE_TYPE_WRITE_BACK,
- ARM_CACHE_TYPE_UNKNOWN
-} ARM_CACHE_TYPE;
-
-typedef enum {
- ARM_CACHE_ARCHITECTURE_UNIFIED,
- ARM_CACHE_ARCHITECTURE_SEPARATE,
- ARM_CACHE_ARCHITECTURE_UNKNOWN
-} ARM_CACHE_ARCHITECTURE;
-
-typedef struct {
- ARM_CACHE_TYPE Type;
- ARM_CACHE_ARCHITECTURE Architecture;
- BOOLEAN DataCachePresent;
- UINTN DataCacheSize;
- UINTN DataCacheAssociativity;
- UINTN DataCacheLineLength;
- BOOLEAN InstructionCachePresent;
- UINTN InstructionCacheSize;
- UINTN InstructionCacheAssociativity;
- UINTN InstructionCacheLineLength;
-} ARM_CACHE_INFO;
-
-/**
- * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
- *
- * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
- * be used in Secure World to distinguished Secure to Non-Secure memory.
- */
-typedef enum {
- ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
- ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
- ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
- ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
- ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
- ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
- ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
- ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
-} ARM_MEMORY_REGION_ATTRIBUTES;
-
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
-
-typedef struct {
- EFI_PHYSICAL_ADDRESS PhysicalBase;
- EFI_VIRTUAL_ADDRESS VirtualBase;
- UINTN Length;
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;
-} ARM_MEMORY_REGION_DESCRIPTOR;
-
-typedef VOID (*CACHE_OPERATION)(VOID);
-typedef VOID (*LINE_OPERATION)(UINTN);
-
-//
-// ARM Processor Mode
-//
-typedef enum {
- ARM_PROCESSOR_MODE_USER = 0x10,
- ARM_PROCESSOR_MODE_FIQ = 0x11,
- ARM_PROCESSOR_MODE_IRQ = 0x12,
- ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
- ARM_PROCESSOR_MODE_ABORT = 0x17,
- ARM_PROCESSOR_MODE_HYP = 0x1A,
- ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,
- ARM_PROCESSOR_MODE_SYSTEM = 0x1F,
- ARM_PROCESSOR_MODE_MASK = 0x1F
-} ARM_PROCESSOR_MODE;
-
-//
-// ARM Cpu IDs
-//
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
-
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
-
-//
-// ARM MP Core IDs
-//
-#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
-#define ARM_CORE_MASK 0xFF
-#define ARM_CLUSTER_MASK (0xFF << 8)
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-// Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
- VOID
- );
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCacheInformation (
- OUT ARM_CACHE_INFO *CacheInfo
- );
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
- VOID
- );
-
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15IdCode (
- VOID
- );
-
-UINT32
-EFIAPI
-Cp15CacheInfo (
- VOID
- );
-
-BOOLEAN
-EFIAPI
-ArmIsMpCore (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
- VOID
- );
-
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCleanDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateInstructionCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateDataCacheEntryByMVA (
- IN UINTN Address
- );
-
-VOID
-EFIAPI
-ArmCleanDataCacheEntryByMVA (
- IN UINTN Address
- );
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCacheEntryByMVA (
- IN UINTN Address
- );
-
-VOID
-EFIAPI
-ArmEnableDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDisableDataCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableInstructionCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDisableInstructionCache (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableMmu (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDisableMmu (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDisableCachesAndMmu (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateInstructionAndDataTlb (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableInterrupts (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDisableInterrupts (
- VOID
- );
-
-BOOLEAN
-EFIAPI
-ArmGetInterruptState (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableFiq (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmDisableFiq (
- VOID
- );
-
-BOOLEAN
-EFIAPI
-ArmGetFiqState (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInvalidateTlb (
- VOID
- );
-
-VOID
-EFIAPI
-ArmUpdateTranslationTableEntry (
- IN VOID *TranslationTableEntry,
- IN VOID *Mva
- );
-
-VOID
-EFIAPI
-ArmSetDomainAccessControl (
- IN UINT32 Domain
- );
-
-VOID
-EFIAPI
-ArmSetTTBR0 (
- IN VOID *TranslationTableBase
- );
-
-VOID *
-EFIAPI
-ArmGetTTBR0BaseAddress (
- VOID
- );
-
-VOID
-EFIAPI
-ArmConfigureMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
- OUT UINTN *TranslationTableSize OPTIONAL
- );
-
-BOOLEAN
-EFIAPI
-ArmMmuEnabled (
- VOID
- );
-
-VOID
-EFIAPI
-ArmSwitchProcessorMode (
- IN ARM_PROCESSOR_MODE Mode
- );
-
-ARM_PROCESSOR_MODE
-EFIAPI
-ArmProcessorMode (
- VOID
- );
-
-VOID
-EFIAPI
-ArmEnableBranchPrediction (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDisableBranchPrediction (
- VOID
- );
-
-VOID
-EFIAPI
-ArmSetLowVectors (
- VOID
- );
-
-VOID
-EFIAPI
-ArmSetHighVectors (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDataMemoryBarrier (
- VOID
- );
-
-VOID
-EFIAPI
-ArmDataSyncronizationBarrier (
- VOID
- );
-
-VOID
-EFIAPI
-ArmInstructionSynchronizationBarrier (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteVBar (
- IN UINT32 VectorBase
- );
-
-UINT32
-EFIAPI
-ArmReadVBar (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteAuxCr (
- IN UINT32 Bit
- );
-
-UINT32
-EFIAPI
-ArmReadAuxCr (
- VOID
- );
-
-VOID
-EFIAPI
-ArmSetAuxCrBit (
- IN UINT32 Bits
- );
-
-VOID
-EFIAPI
-ArmUnsetAuxCrBit (
- IN UINT32 Bits
- );
-
-VOID
-EFIAPI
-ArmCallSEV (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCallWFE (
- VOID
- );
-
-VOID
-EFIAPI
-ArmCallWFI (
- VOID
- );
-
-UINTN
-EFIAPI
-ArmReadMpidr (
- VOID
- );
-
-UINT32
-EFIAPI
-ArmReadCpacr (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteCpacr (
- IN UINT32 Access
- );
-
-VOID
-EFIAPI
-ArmEnableVFP (
- VOID
- );
-
-UINT32
-EFIAPI
-ArmReadNsacr (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteNsacr (
- IN UINT32 SetWayFormat
- );
-
-UINT32
-EFIAPI
-ArmReadScr (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteScr (
- IN UINT32 SetWayFormat
- );
-
-UINT32
-EFIAPI
-ArmReadMVBar (
- VOID
- );
-
-VOID
-EFIAPI
-ArmWriteMVBar (
- IN UINT32 VectorMonitorBase
- );
-
-UINT32
-EFIAPI
-ArmReadSctlr (
- VOID
- );
-
-#endif // __ARM_LIB__
+/** @file\r
+\r
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
+\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_LIB__\r
+#define __ARM_LIB__\r
+\r
+#include <Uefi/UefiBaseType.h>\r
+\r
+#ifdef MDE_CPU_ARM\r
+ #include <Chipset/ArmV7.h>\r
+#elif defined(MDE_CPU_AARCH64)\r
+ #include <Chipset/AArch64.h>\r
+#else\r
+ #error "Unknown chipset."\r
+#endif\r
+\r
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
+ EFI_MEMORY_UCE)\r
+\r
+/**\r
+ * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
+ *\r
+ * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
+ * be used in Secure World to distinguished Secure to Non-Secure memory.\r
+ */\r
+typedef enum {\r
+ ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
+\r
+ // On some platforms, memory mapped flash region is designed as not supporting\r
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
+ // need.\r
+ // Do NOT use below two attributes if you are not sure.\r
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
+\r
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
+} ARM_MEMORY_REGION_ATTRIBUTES;\r
+\r
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
+\r
+typedef struct {\r
+ EFI_PHYSICAL_ADDRESS PhysicalBase;\r
+ EFI_VIRTUAL_ADDRESS VirtualBase;\r
+ UINT64 Length;\r
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
+} ARM_MEMORY_REGION_DESCRIPTOR;\r
+\r
+typedef VOID (*CACHE_OPERATION)(VOID);\r
+typedef VOID (*LINE_OPERATION)(UINTN);\r
+\r
+//\r
+// ARM Processor Mode\r
+//\r
+typedef enum {\r
+ ARM_PROCESSOR_MODE_USER = 0x10,\r
+ ARM_PROCESSOR_MODE_FIQ = 0x11,\r
+ ARM_PROCESSOR_MODE_IRQ = 0x12,\r
+ ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
+ ARM_PROCESSOR_MODE_ABORT = 0x17,\r
+ ARM_PROCESSOR_MODE_HYP = 0x1A,\r
+ ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
+ ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
+ ARM_PROCESSOR_MODE_MASK = 0x1F\r
+} ARM_PROCESSOR_MODE;\r
+\r
+//\r
+// ARM Cpu IDs\r
+//\r
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
+\r
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
+\r
+//\r
+// ARM MP Core IDs\r
+//\r
+#define ARM_CORE_AFF0 0xFF\r
+#define ARM_CORE_AFF1 (0xFF << 8)\r
+#define ARM_CORE_AFF2 (0xFF << 16)\r
+#define ARM_CORE_AFF3 (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmCacheWritebackGranule (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmIsArchTimerImplemented (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr0 (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr1 (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmCacheInfo (\r
+ VOID\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmIsMpCore (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCache (\r
+ VOID\r
+ );\r
+\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateInstructionCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryByMVA (\r
+ IN UINTN Address\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryToPoUByMVA (\r
+ IN UINTN Address\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
+ IN UINTN Address\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA (\r
+IN UINTN Address\r
+);\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryByMVA (\r
+ IN UINTN Address\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableDataCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableDataCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableInstructionCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableInstructionCache (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableMmu (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableMmu (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableCachesAndMmu (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableCachesAndMmu (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableInterrupts (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableInterrupts (\r
+ VOID\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGetInterruptState (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableIrq (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableFiq (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmDisableFiq (\r
+ VOID\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmGetFiqState (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r
+VOID\r
+EFIAPI\r
+ArmInvalidateTlb (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUpdateTranslationTableEntry (\r
+ IN VOID *TranslationTableEntry,\r
+ IN VOID *Mva\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetDomainAccessControl (\r
+ IN UINT32 Domain\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetTTBR0 (\r
+ IN VOID *TranslationTableBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetTTBCR (\r
+ IN UINT32 Bits\r
+ );\r
+\r
+VOID *\r
+EFIAPI\r
+ArmGetTTBR0BaseAddress (\r
+ VOID\r
+ );\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmMmuEnabled (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableBranchPrediction (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableBranchPrediction (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetLowVectors (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetHighVectors (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDataMemoryBarrier (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmDataSynchronizationBarrier (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmInstructionSynchronizationBarrier (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteVBar (\r
+ IN UINTN VectorBase\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadVBar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteAuxCr (\r
+ IN UINT32 Bit\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadAuxCr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetAuxCrBit (\r
+ IN UINT32 Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetAuxCrBit (\r
+ IN UINT32 Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCallSEV (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCallWFE (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCallWFI (\r
+\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadMpidr (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadMidr (\r
+ VOID\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadCpacr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpacr (\r
+ IN UINT32 Access\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableVFP (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Get the Secure Configuration Register value\r
+\r
+ @return Value read from the Secure Configuration Register\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+ArmReadScr (\r
+ VOID\r
+ );\r
+\r
+/**\r
+ Set the Secure Configuration Register\r
+\r
+ @param Value Value to write to the Secure Configuration Register\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+ArmWriteScr (\r
+ IN UINT32 Value\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadMVBar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteMVBar (\r
+ IN UINT32 VectorMonitorBase\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmReadSctlr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteSctlr (\r
+ IN UINT32 Value\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadHVBar (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteHVBar (\r
+ IN UINTN HypModeVectorBase\r
+ );\r
+\r
+\r
+//\r
+// Helper functions for accessing CPU ACTLR\r
+//\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCpuActlr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpuActlr (\r
+ IN UINTN Val\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
+//\r
+// Accessors for the architected generic timer registers\r
+//\r
+\r
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntFrq (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntFrq (\r
+ UINTN FreqInHz\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntPct (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntkCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntkCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCt (\r
+ VOID\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntpCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvOff (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvOff (\r
+ UINT64 Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGetPhysicalAddressBits (\r
+ VOID\r
+ );\r
+\r
+#endif // __ARM_LIB__\r
projects / mirror_edk2.git / blobdiff