/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
-#ifdef ARM_CPU_ARMv6\r
-#include <Chipset/ARM1176JZ-S.h>\r
+#ifdef MDE_CPU_ARM\r
+ #include <Chipset/ArmV7.h>\r
+#elif defined(MDE_CPU_AARCH64)\r
+ #include <Chipset/AArch64.h>\r
#else\r
-#include <Chipset/ArmV7.h>\r
+ #error "Unknown chipset."\r
#endif\r
\r
-typedef enum {\r
- ARM_CACHE_TYPE_WRITE_BACK,\r
- ARM_CACHE_TYPE_UNKNOWN\r
-} ARM_CACHE_TYPE;\r
-\r
-typedef enum {\r
- ARM_CACHE_ARCHITECTURE_UNIFIED,\r
- ARM_CACHE_ARCHITECTURE_SEPARATE,\r
- ARM_CACHE_ARCHITECTURE_UNKNOWN\r
-} ARM_CACHE_ARCHITECTURE;\r
-\r
-typedef struct {\r
- ARM_CACHE_TYPE Type;\r
- ARM_CACHE_ARCHITECTURE Architecture;\r
- BOOLEAN DataCachePresent;\r
- UINTN DataCacheSize;\r
- UINTN DataCacheAssociativity;\r
- UINTN DataCacheLineLength;\r
- BOOLEAN InstructionCachePresent;\r
- UINTN InstructionCacheSize;\r
- UINTN InstructionCacheAssociativity;\r
- UINTN InstructionCacheLineLength;\r
-} ARM_CACHE_INFO;\r
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+ EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
+ EFI_MEMORY_UCE)\r
\r
/**\r
* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
+\r
+ // On some platforms, memory mapped flash region is designed as not supporting\r
+ // shareable attribute, so WRITE_BACK_NONSHAREABLE is added for such special\r
+ // need.\r
+ // Do NOT use below two attributes if you are not sure.\r
+ ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE,\r
+ ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE,\r
+\r
ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
typedef struct {\r
EFI_PHYSICAL_ADDRESS PhysicalBase;\r
EFI_VIRTUAL_ADDRESS VirtualBase;\r
- UINTN Length;\r
+ UINT64 Length;\r
ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
//\r
// ARM MP Core IDs\r
//\r
-#define ARM_CORE_MASK 0xFF\r
-#define ARM_CLUSTER_MASK (0xFF << 8)\r
+#define ARM_CORE_AFF0 0xFF\r
+#define ARM_CORE_AFF1 (0xFF << 8)\r
+#define ARM_CORE_AFF2 (0xFF << 16)\r
+#define ARM_CORE_AFF3 (0xFFULL << 32)\r
+\r
+#define ARM_CORE_MASK ARM_CORE_AFF0\r
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
-// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
-// Position = (ClusterId * 4) + CoreId\r
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
- VOID\r
- );\r
-\r
-ARM_CACHE_ARCHITECTURE\r
+UINTN\r
EFIAPI\r
-ArmCacheArchitecture (\r
+ArmDataCacheLineLength (\r
VOID\r
);\r
\r
-VOID\r
-EFIAPI\r
-ArmCacheInformation (\r
- OUT ARM_CACHE_INFO *CacheInfo\r
- );\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
- VOID\r
- );\r
- \r
UINTN\r
EFIAPI\r
-ArmDataCacheSize (\r
+ArmInstructionCacheLineLength (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
-ArmDataCacheAssociativity (\r
+ArmCacheWritebackGranule (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
-ArmDataCacheLineLength (\r
- VOID\r
- );\r
- \r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
+ArmIsArchTimerImplemented (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
-ArmInstructionCacheSize (\r
+ArmReadIdPfr0 (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
-ArmInstructionCacheAssociativity (\r
+ArmReadIdPfr1 (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
-ArmInstructionCacheLineLength (\r
- VOID\r
- );\r
- \r
-UINT32\r
-EFIAPI\r
-Cp15IdCode (\r
- VOID\r
- );\r
- \r
-UINT32\r
-EFIAPI\r
-Cp15CacheInfo (\r
+ArmCacheInfo (\r
VOID\r
);\r
\r
\r
VOID\r
EFIAPI\r
-ArmCleanDataCacheToPoU (\r
+ArmInvalidateInstructionCache (\r
VOID\r
);\r
\r
VOID\r
EFIAPI\r
-ArmInvalidateInstructionCache (\r
- VOID\r
+ArmInvalidateDataCacheEntryByMVA (\r
+ IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
-ArmInvalidateDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA (\r
IN UINTN Address\r
);\r
\r
VOID\r
EFIAPI\r
-ArmCleanDataCacheEntryByMVA (\r
+ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
IN UINTN Address\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA (\r
+IN UINTN Address\r
+);\r
+\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
IN UINTN Address\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
ArmDisableInstructionCache (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
\r
VOID\r
EFIAPI\r
-ArmDisableCachesAndMmu (\r
+ArmEnableCachesAndMmu (\r
VOID\r
);\r
\r
VOID\r
EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
+ArmDisableCachesAndMmu (\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
UINTN\r
EFIAPI\r
-ArmDisableIrq (\r
+ArmDisableAsynchronousAbort (\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+ VOID\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
ArmDisableFiq (\r
VOID\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
VOID\r
);\r
\r
+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
IN VOID *TranslationTableEntry,\r
IN VOID *Mva\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
IN VOID *TranslationTableBase\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmSetTTBCR (\r
+ IN UINT32 Bits\r
+ );\r
+\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
VOID\r
);\r
\r
-RETURN_STATUS\r
-EFIAPI\r
-ArmConfigureMmu (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
- OUT UINTN *TranslationTableSize OPTIONAL\r
- );\r
- \r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
VOID\r
);\r
- \r
-VOID\r
-EFIAPI\r
-ArmSwitchProcessorMode (\r
- IN ARM_PROCESSOR_MODE Mode\r
- );\r
\r
-ARM_PROCESSOR_MODE\r
-EFIAPI\r
-ArmProcessorMode (\r
- VOID\r
- );\r
- \r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
ArmDataMemoryBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
- IN UINT32 VectorBase\r
+ IN UINTN VectorBase\r
);\r
\r
-UINT32\r
+UINTN\r
EFIAPI\r
ArmReadVBar (\r
VOID\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
+\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmReadMidr (\r
+ VOID\r
+ );\r
+\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
VOID\r
);\r
\r
-UINT32\r
-EFIAPI\r
-ArmReadNsacr (\r
- VOID\r
- );\r
+/**\r
+ Get the Secure Configuration Register value\r
\r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
- IN UINT32 SetWayFormat\r
- );\r
+ @return Value read from the Secure Configuration Register\r
\r
+**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
VOID\r
);\r
\r
+/**\r
+ Set the Secure Configuration Register\r
+\r
+ @param Value Value to write to the Secure Configuration Register\r
+\r
+**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
- IN UINT32 SetWayFormat\r
+ IN UINT32 Value\r
);\r
\r
UINT32\r
VOID\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmWriteSctlr (\r
+ IN UINT32 Value\r
+ );\r
+\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
IN UINTN HypModeVectorBase\r
);\r
\r
+\r
+//\r
+// Helper functions for accessing CPU ACTLR\r
+//\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCpuActlr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpuActlr (\r
+ IN UINTN Val\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
+//\r
+// Accessors for the architected generic timer registers\r
+//\r
+\r
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
+#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntFrq (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntFrq (\r
+ UINTN FreqInHz\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntPct (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntkCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntkCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntpCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvTval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvTval (\r
+ UINTN Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCntvCtl (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCtl (\r
+ UINTN Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCt (\r
+ VOID\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntpCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntpCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvCval (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvCval (\r
+ UINT64 Val\r
+ );\r
+\r
+UINT64\r
+EFIAPI\r
+ArmReadCntvOff (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCntvOff (\r
+ UINT64 Val\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGetPhysicalAddressBits (\r
+ VOID\r
+ );\r
+\r
#endif // __ARM_LIB__\r
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