try to reuse existing case entries if possible.\r
\r
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+ Copyright (c) 2021, Arm Limited. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
// in the instruction address and you get back the aligned answer\r
//\r
UINT32\r
-PCAlign4 (\r
+PcAlign4 (\r
IN UINT32 Data\r
)\r
{\r
UINT32 Index;\r
UINT32 Offset;\r
UINT16 Rd, Rn, Rm, Rt, Rt2;\r
- BOOLEAN H1, H2, imod;\r
+ BOOLEAN H1Bit; // H1\r
+ BOOLEAN H2Bit; // H2\r
+ BOOLEAN IMod; // imod\r
//BOOLEAN ItFlag;\r
- UINT32 PC, Target, msbit, lsbit;\r
+ UINT32 Pc, Target, MsBit, LsBit;\r
CHAR8 *Cond;\r
- BOOLEAN S, J1, J2, P, U, W;\r
- UINT32 coproc, opc1, opc2, CRd, CRn, CRm;\r
+ BOOLEAN Sign; // S\r
+ BOOLEAN J1Bit; // J1\r
+ BOOLEAN J2Bit; // J2\r
+ BOOLEAN Pre; // P\r
+ BOOLEAN UAdd; // U\r
+ BOOLEAN WriteBack; // W\r
+ UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;\r
UINT32 Mask;\r
\r
OpCodePtr = *OpCodePtrPtr;\r
Rd = OpCode & 0x7;\r
Rn = (OpCode >> 3) & 0x7;\r
Rm = (OpCode >> 6) & 0x7;\r
- H1 = (OpCode & BIT7) != 0;\r
- H2 = (OpCode & BIT6) != 0;\r
- imod = (OpCode & BIT4) != 0;\r
- PC = (UINT32)(UINTN)OpCodePtr;\r
+ H1Bit = (OpCode & BIT7) != 0;\r
+ H2Bit = (OpCode & BIT6) != 0;\r
+ IMod = (OpCode & BIT4) != 0;\r
+ Pc = (UINT32)(UINTN)OpCodePtr;\r
\r
// Increment by the minimum instruction size, Thumb2 could be bigger\r
*OpCodePtrPtr += 1;\r
case LOAD_STORE_FORMAT3:\r
// A6.5.1 <Rd>, [PC, #<8_bit_offset>]\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);\r
return;\r
case LOAD_STORE_FORMAT4:\r
// Rt, [SP, #imm8]\r
Cond = gCondition[(OpCode >> 8) & 0xf];\r
Buf[Offset-5] = *Cond++;\r
Buf[Offset-4] = *Cond;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));\r
return;\r
case UNCONDITIONAL_BRANCH_SHORT:\r
// A6.3.2 B <target_address>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", PC + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));\r
return;\r
\r
case BRANCH_EXCHANGE:\r
// A6.3.3 BX|BLX <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2 ? 8:0)]);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);\r
return;\r
\r
case DATA_FORMAT1:\r
return;\r
case DATA_FORMAT8:\r
// A6.4.3 <Rd>|<Rn>, <Rm>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1 ? 8:0)], gReg[Rn | (H2 ? 8:0)]);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);\r
return;\r
\r
case CPS_FORMAT:\r
// A7.1.24\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", imod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");\r
return;\r
\r
case ENDIAN_FORMAT:\r
case DATA_CBZ:\r
// CB{N}Z <Rn>, <Lable>\r
Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);\r
return;\r
\r
case ADR_FORMAT:\r
// ADR <Rd>, <Label>\r
Target = (OpCode & 0xff) << 2;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);\r
return;\r
\r
case IT_BLOCK:\r
Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1\r
Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S\r
Target = SignExtend32 (Target, BIT20);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
return;\r
case B_T4:\r
// S:I1:I2:imm10:imm11:0\r
Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);\r
- S = (OpCode32 & BIT26) == BIT26;\r
- J1 = (OpCode32 & BIT13) == BIT13;\r
- J2 = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2 ^ S) ? BIT22 : 0); // I2\r
- Target |= (!(J1 ^ S) ? BIT23 : 0); // I1\r
- Target |= (S ? BIT24 : 0); // S\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1\r
+ Target |= (Sign ? BIT24 : 0); // S\r
Target = SignExtend32 (Target, BIT24);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);\r
return;\r
\r
case BL_T2:\r
// BLX S:I1:I2:imm10:imm11:0\r
Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);\r
- S = (OpCode32 & BIT26) == BIT26;\r
- J1 = (OpCode32 & BIT13) == BIT13;\r
- J2 = (OpCode32 & BIT11) == BIT11;\r
- Target |= (!(J2 ^ S) ? BIT23 : 0); // I2\r
- Target |= (!(J1 ^ S) ? BIT24 : 0); // I1\r
- Target |= (S ? BIT25 : 0); // S\r
+ Sign = (OpCode32 & BIT26) == BIT26;\r
+ J1Bit = (OpCode32 & BIT13) == BIT13;\r
+ J2Bit = (OpCode32 & BIT11) == BIT11;\r
+ Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2\r
+ Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1\r
+ Target |= (Sign ? BIT25 : 0); // S\r
Target = SignExtend32 (Target, BIT25);\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);\r
return;\r
\r
case POP_T2:\r
\r
case STM_FORMAT:\r
// <Rn>{!}, <registers>\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], W ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));\r
return;\r
\r
case LDM_REG_IMM12_SIGNED:\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PCAlign4 (PC) + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);\r
return;\r
\r
case LDM_REG_INDIRECT_LSL:\r
\r
case LDM_REG_IMM8:\r
// <rt>, [<rn>, {, #<imm8>}]{!}\r
- W = (OpCode32 & BIT8) == BIT8;\r
- U = (OpCode32 & BIT9) == BIT9;\r
- P = (OpCode32 & BIT10) == BIT10;\r
+ WriteBack = (OpCode32 & BIT8) == BIT8;\r
+ UAdd = (OpCode32 & BIT9) == BIT9;\r
+ Pre = (OpCode32 & BIT10) == BIT10;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);\r
- if (P) {\r
+ if (Pre) {\r
if ((OpCode32 & 0xff) == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");\r
}\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);\r
}\r
return;\r
\r
case LDRD_REG_IMM8_SIGNED:\r
// LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}\r
- P = (OpCode32 & BIT24) == BIT24; // index = P\r
- U = (OpCode32 & BIT23) == BIT23;\r
- W = (OpCode32 & BIT21) == BIT21;\r
+ Pre = (OpCode32 & BIT24) == BIT24; // index = P\r
+ UAdd = (OpCode32 & BIT23) == BIT23;\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);\r
- if (P) {\r
+ if (Pre) {\r
if ((OpCode32 & 0xff) == 0) {\r
AsciiSPrint (&Buf[Offset], Size - Offset, "]");\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-", (OpCode32 & 0xff) << 2, W?"!":"");\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");\r
}\r
} else {\r
if ((OpCode32 & 0xff) != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", U?"":"-", (OpCode32 & 0xff) << 2);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);\r
}\r
}\r
return;\r
// U == 0 means subtrack, U == 1 means add\r
Target = -Target;\r
}\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], PC + 4 + Target);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);\r
return;\r
\r
case LDREXB:\r
\r
case SRS_FORMAT:\r
// SP{!}, #<mode>\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", W?"!":"", OpCode32 & 0x1f);\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);\r
return;\r
\r
case RFE_FORMAT:\r
// <Rn>{!}\r
- W = (OpCode32 & BIT21) == BIT21;\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], W?"!":"");\r
+ WriteBack = (OpCode32 & BIT21) == BIT21;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");\r
return;\r
\r
case ADD_IMM12:\r
// ADDR <Rd>, <label>\r
Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {\r
- Target = PCAlign4 (PC) - Target;\r
+ Target = PcAlign4 (Pc) - Target;\r
} else {\r
- Target = PCAlign4 (PC) + Target;\r
+ Target = PcAlign4 (Pc) + Target;\r
}\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);\r
return;\r
\r
case BFC_THUMB2:\r
// BFI <Rd>, <Rn>, #<lsb>, #<width>\r
- msbit = OpCode32 & 0x1f;\r
- lsbit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
+ MsBit = OpCode32 & 0x1f;\r
+ LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);\r
if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){\r
// BFC <Rd>, #<lsb>, #<width>\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], lsbit, msbit - lsbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);\r
} else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit - lsbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);\r
} else {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], lsbit, msbit + 1);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);\r
}\r
return;\r
\r
case CPD_THUMB2:\r
// <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
- opc2 = (OpCode32 >> 5) & 0x7;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
CRd = (OpCode32 >> 12) & 0xf;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", coproc, opc1, CRd, CRn, CRm);\r
- if (opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
}\r
return;\r
\r
case MRC_THUMB2:\r
// MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
- opc2 = (OpCode32 >> 5) & 0x7;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
+ Opc2 = (OpCode32 >> 5) & 0x7;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);\r
- if (opc2 != 0) {\r
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);\r
+ if (Opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);\r
}\r
return;\r
\r
case MRRC_THUMB2:\r
// MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
- coproc = (OpCode32 >> 8) & 0xf;\r
- opc1 = (OpCode32 >> 20) & 0xf;\r
+ Coproc = (OpCode32 >> 8) & 0xf;\r
+ Opc1 = (OpCode32 >> 20) & 0xf;\r
CRn = (OpCode32 >> 16) & 0xf;\r
CRm = OpCode32 & 0xf;\r
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);\r
return;\r
\r
case THUMB2_2REGS:\r
projects / mirror_edk2.git / blobdiff