#define ADD_IMM5_2REG 228\r
#define CPD_THUMB2 229\r
#define THUMB2_4REGS 230\r
+#define ADD_IMM12_1REG 231\r
+#define THUMB2_IMM16 232\r
+#define MRC_THUMB2 233 \r
+#define MRRC_THUMB2 234 \r
+#define THUMB2_MRS 235\r
+#define THUMB2_MSR 236\r
+\r
+\r
\r
\r
typedef struct {\r
{ "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>\r
{ "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}\r
\r
+ { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>\r
+ { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>\r
+ { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>\r
+ \r
{ "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>\r
{ "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}\r
{ "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>\r
{ "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
{ "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>\r
\r
+ { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
+ { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>\r
+\r
+ { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR\r
+ { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>\r
+\r
{ "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX\r
\r
{ "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>\r
{ "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>\r
{ "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>\r
{ "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS },// SMLAWB <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS },// SMLAWT <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS },// SMLSD <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS },// SMLSDX <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS },// SMMLA <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS },// SMMLAR <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS },// SMMLS <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS },// SMMLSR <Rd>, <Rn>, <Rm>, <Ra>\r
- { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS },// USADA8 <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS },// SMLAD <Rd>, <Rn>, <Rm>, <Ra>\r
- { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS },// SMLADX <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>\r
+ { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>\r
\r
\r
{ "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target); \r
return;\r
\r
+ case ADD_IMM12_1REG:\r
+ // MOV{S} <Rd>, #<const> i:imm3:imm8\r
+ if ((OpCode32 & BIT20) == BIT20) {\r
+ Buf[Offset - 3] = 'S'; // assume %-6a\r
+ }\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); \r
+ return;\r
+\r
+ case THUMB2_IMM16:\r
+ // MOVW <Rd>, #<const> i:imm3:imm8\r
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);\r
+ Target |= ((OpCode32 >> 4) & 0xf0000);\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target); \r
+ return;\r
+\r
case ADD_IMM5:\r
// ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2\r
if ((OpCode32 & BIT20) == BIT20) {\r
}\r
return;\r
\r
+ case MRC_THUMB2:\r
+ // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>\r
+ coproc = (OpCode32 >> 8) & 0xf;\r
+ opc1 = (OpCode32 >> 20) & 0xf;\r
+ opc2 = (OpCode32 >> 5) & 0x7;\r
+ CRn = (OpCode32 >> 16) & 0xf;\r
+ CRm = OpCode32 & 0xf;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", coproc, opc1, gReg[Rt], CRn, CRm);\r
+ if (opc2 != 0) {\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", opc2);\r
+ }\r
+ return; \r
+\r
+ case MRRC_THUMB2:\r
+ // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>\r
+ coproc = (OpCode32 >> 8) & 0xf;\r
+ opc1 = (OpCode32 >> 20) & 0xf;\r
+ CRn = (OpCode32 >> 16) & 0xf;\r
+ CRm = OpCode32 & 0xf;\r
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", coproc, opc1, gReg[Rt], gReg[Rt2], CRm);\r
+ return; \r
+\r
case THUMB2_2REGS:\r
// <Rd>, <Rm>\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);\r
AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);\r
return;\r
\r
+ case THUMB2_MRS:\r
+ // MRS <Rd>, CPSR\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);\r
+ return;\r
+ \r
+ case THUMB2_MSR:\r
+ // MRS CPSR_<fields>, <Rd>\r
+ Target = (OpCode32 >> 10) & 3;\r
+ AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "":"f", (Target & 1) == 0 ? "":"s", gReg[Rd]);\r
+ return;\r
+\r
case THUMB2_NO_ARGS:\r
default:\r
break;\r
projects / mirror_edk2.git / blobdiff