3:mrs x0, sctlr_el3\r
4:ret\r
\r
+ASM_FUNC(ArmWriteSctlr)\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1:msr sctlr_el1, x0\r
+ ret\r
+2:msr sctlr_el2, x0\r
+ ret\r
+3:msr sctlr_el3, x0\r
+4:ret\r
+\r
+ASM_FUNC(ArmGetPhysicalAddressBits)\r
+ mrs x0, id_aa64mmfr0_el1\r
+ adr x1, .LPARanges\r
+ and x0, x0, #0xf\r
+ ldrb w0, [x1, x0]\r
+ ret\r
+\r
+//\r
+// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the\r
+// physical address space support on this CPU:\r
+// 0 == 32 bits, 1 == 36 bits, etc etc\r
+// 7 and up are reserved\r
+//\r
+.LPARanges:\r
+ .byte 32, 36, 40, 42, 44, 48, 52, 0\r
+ .byte 0, 0, 0, 0, 0, 0, 0, 0\r
+\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r