ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm11 / Arm11Support.asm

diff --git a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
index 8c27093045b9e6e534203977e64f5403369e57e5..53283d1eea2a388c0e656a6ddd91c47747d1dcf1 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
+++ b/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
@@ -1,4 +1,4 @@
-//------------------------------------------------------------------------------ \r
+//------------------------------------------------------------------------------\r
 //\r
 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 //\r
@@ -43,12 +43,12 @@ XP_ON       EQU     ( 0x1:SHL:23 )
 \r
 \r
 ArmInvalidateDataCacheEntryByMVA\r
-  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           \r
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
   bx      lr\r
 \r
 \r
 ArmCleanDataCacheEntryByMVA\r
-  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     \r
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
   bx      lr\r
 \r
 \r
@@ -105,7 +105,7 @@ ArmEnableDataCache
   ORR     R0,R0,R1              ;Set C bit\r
   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
   BX      LR\r
-    \r
+\r
 ArmDisableDataCache\r
   LDR     R1,=DC_ON\r
   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
@@ -119,7 +119,7 @@ ArmEnableInstructionCache
   ORR     R0,R0,R1             ;Set I bit\r
   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
   BX      LR\r
-  \r
+\r
 ArmDisableInstructionCache\r
   LDR     R1,=IC_ON\r
   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
@@ -141,17 +141,17 @@ ArmDisableBranchPrediction
 \r
 ASM_PFX(ArmDataMemoryBarrier):\r
   mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #5 \r
+  mcr P15, #0, R0, C7, C10, #5\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmDataSyncronizationBarrier):\r
   mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #4 \r
+  mcr P15, #0, R0, C7, C10, #4\r
   bx      LR\r
-  \r
+\r
 ASM_PFX(ArmInstructionSynchronizationBarrier):\r
   MOV R0, #0\r
-  MCR P15, #0, R0, C7, C5, #4 \r
+  MCR P15, #0, R0, C7, C5, #4\r
   bx      LR\r
 \r
     END\r